# StaticSkuDataDxeLightningRidgeEXECB3

## Function Table

| Address | Name | Description |
|---------|------|-------------|
|  | **DebugReport** |  |
|  | **ReadUnaligned64** |  |
|  | **CompareHobGuid** |  |
|  | **DebugWrite** |  |
|  | **ModuleEntryPoint** |  |
| Protocol | **GUIDs** |  |
| STATIC | **CONST EFI_GUID  mPlatformProtocolGuid =** |  |
| Globals | **// -------------------------------------------------------------------------** |  |
| EFI_HANDLE | **gImageHandle      = NULL;  ///< Offset 0xF550** |  |
| Debug | **Assertion Strings  (offset 0x780 - 0x3F00)** |  |
| STATIC | **CONST CHAR8  mAssertEfiError[]       = "\nASSERT_EFI_ERROR (Status = %r)\n";** |  |
| ACPI | **namespace method names for SKU data access** |  |
| STATIC | **CONST CHAR8  mAcpiNameCCT0[] = "_SB_.CCT0";** |  |
| Static | **Data Section Layout  (0x4080 - 0xF580)** |  |
| The | **.data section contains the platform HOB descriptor block followed** |  |
| by | **the UMPT config table, UMPT data entries, PIRQ routing, core family** |  |
| Platform | **HOB descriptor at 0x40A0.** |  |
| PIRQ | **protocol GUID, tag 'PIRQ', version, PIRQ data ptr** |  |
| ACPI | **processor GUID, NULL sentinel, size.** |  |
| STATIC | **CONST struct {** |  |
| UMPT | **configuration table at 0x9040.** |  |
| Each | **entry: { UINT64 DataOffset, UINT64 DataSize }** |  |
| STATIC | **CONST TABLE_DESCRIPTOR  mUmptConfigTable[] = {** |  |
| Socket | **memory topology (59 bytes)** |  |
| IOAPIC | **interrupt routing (211 bytes)** |  |
| Socket | **core/thread map (25 bytes)** |  |
| Config | **sentinel (2 bytes)** |  |
| UMPT | **data entries at 0x9060.** |  |
| STATIC | **CONST TABLE_DESCRIPTOR  mUmptDataTable[] = {** |  |
| Socket | **core topology map** |  |
| Config | **sentinel** |  |
| Core | **Family Hierarchy (CFH)** |  |
| Core | **Configuration Table (CCT)** |  |
| ACPI | **Processor Data block at 0x9020.** |  |
| PIRQ | **data table header at 0x40D8.** |  |
| Memory | **socket topology data at 0xD690 (59+ bytes).** |  |
| UINT8 | **SubType; UINT8 ChannelMap[3]; UINT8 Reserved2[3] }** |  |
| STATIC | **CONST UINT8  mSocketMemoryTopology[] = {** |  |
| Socket | **0, DDR5 (Type=0x0A), channels [4,5,6] (A/B/C)** |  |
| Socket | **1, Type=0x0B, channels rotated** |  |
| Socket | **2, Type=0x0C** |  |
| Socket | **3, Type=0x0D** |  |
| Socket | **4, Type=0x0E** |  |
| Socket | **5, Type=0x0F** |  |
| Socket | **6, Type=0x10** |  |
| Socket | **core/thread topology at 0x9110 (25 bytes).** |  |
| STATIC | **CONST UINT8  mSocketCoreTopology[] = {** |  |
| Socket | **0, APIC base 0xFEC00000** |  |
| Type | **0x20, count=9** |  |
| Socket | **1, APIC base 0xFEC08000,...** |  |
| IOAPIC | **interrupt routing data at 0xC2C0 (211 bytes).** |  |
| STATIC | **CONST UINT8  mIoApicRoutingData[] = {** |  |
| Entry | **0: flags=0xFF, ioapic=0x00, intin=0x09, dev=0x07** |  |
| Core | **Family Hierarchy at 0xDB60 (275 bytes).** |  |
| UINT8 | **Flags, UINT8 ApicId, UINT16 Reserved2, UINT32 Caps}** |  |
| STATIC | **CONST UINT8  mCoreFamilyHierarchy[] = {** |  |
| Clusters | **0-10, each with type 0x1F (standard core)** |  |
| Cluster | **1: ApicId=1** |  |
| Cluster | **2: ApicId=2** |  |
| Cluster | **3: ApicId=3** |  |
| Cluster | **4: ApicId=4** |  |
| Cluster | **5: ApicId=5** |  |
| Cluster | **6: ApicId=6** |  |
| Cluster | **7: ApicId=7** |  |
| Cluster | **8: ApicId=8, caps=1** |  |
| Cluster | **9: ApicId=9** |  |
| Cluster | **A: ApicId=0xA** |  |
| Core | **Configuration Table (CCT) at 0xBD80 (67 bytes).** |  |
| UINT8 | **Flags, UINT8 ApicCluster, UINT8 CoreMap[4]** |  |
| UINT32 | **Reserved2}** |  |
| STATIC | **CONST UINT8  mCoreConfigTable[] = {** |  |
| Cluster | **0, 4-way interleave: cores [16,17,18,19]** |  |
| Cluster | **1, rotated: [17,18,19,16]** |  |
| Cluster | **2, rotated: [18,19,16,17]** |  |
| Cluster | **3, rotated: [19,16,17,18]** |  |
| UMPT | **entry 1 sentinel (2 bytes) at 0xDB30.** |  |
| STATIC | **CONST UINT8  mConfigSentinel[] = { 0x00, 0x00 };** |  |
| PIRQ | **routing entries header at 0x90D8.** |  |
| STATIC | **CONST TABLE_DESCRIPTOR  mPirqDataEntries[] = {** |  |
| PIRQ | **entry 0: 7 bytes header** |  |
| PIRQ | **entry 1** |  |
| PIRQ | **entry 2: large routing table** |  |
| Terminator | **};** |  |
| PIRQ | **routing entry at 0xBD70 (7 bytes header).** |  |
| STATIC | **CONST UINT8  mPirqRoutingHeader[] = {** |  |
| Helper | **Functions** |  |
| Protocol | **function at offset +8: DebugReport(file, line, desc)** |  |
| DebugFunc | **= *(UINT64 (**)(CONST CHAR8 *, UINTN, CONST CHAR8 *))(** |  |
| Walk | **the system configuration table.** |  |
| gST | **+ 104 = NumberOfTableEntries (offset 0x68 in EFI_SYSTEM_TABLE)** |  |
| gST | **+ 112 = ConfigurationTable  (offset 0x70)** |  |
| HobCount | **= *(UINTN *)((UINT8 *)gST + 104);** |  |
| Found | **-- the data pointer is at offset +16 in the table entry.** |  |
| gHobList | **= *(VOID **)((UINT8 *)TableEntry + 16);** |  |
| Read | **CMOS register to determine debug verbosity.** |  |
| Index | **register 0x70, data register 0x71.** |  |
| CmosValue | **= __inbyte (0x70);** |  |
| Read | **debug level from platform-specific memory location.** |  |
| CmosIndex | **= (*(volatile UINT8 *)0xFDAF0490 & 2) | 1;** |  |
| DEBUG_INFO | **} else {** |  |
| DEBUG_VERBOSE | **}** |  |
| Entry | **Point** |  |
| Store | **global UEFI handles for library-style access.** |  |
| gImageHandle | **= ImageHandle;** |  |
| Initialize | **the platform protocol and HOB list.** |  |
| GetHobList | **(ImageHandle);** |  |
| Locate | **the platform protocol interface.** |  |
| Status | **= gBS->LocateProtocol (** |  |
| Install | **static SKU data protocol.** |  |
| Protocol | **GUID: 0FF8A1CF-A0AB-4AC0-BFC9-34A78F68DD8A** |  |
| Install | **function at offset +16 in the protocol interface.** |  |
| InstallTableFunc | **= (UINT64 (*)(VOID *, VOID *, VOID *, UINT64))(** |  |
| Install | **the Static SKU Data protocol with PIRQ routing info.** |  |
| Status | **= (EFI_STATUS)InstallTableFunc (** |  |
| Install | **the PIRQ routing data table.** |  |
| Install | **the ACPI processor info table.** |  |

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*Generated by HR650X BIOS Decompilation Project*