# OpromUpdateDxeNeonCityFPGA

## Function Table

| Address | Name | Description |
|---------|------|-------------|
|  | **DebugPrint** |  |
|  | **DebugAssert** |  |
|  | **ReadUnaligned64** |  |
|  | **IsGuidEqual** |  |
|  | **PcieSlotChecker** |  |
|  | **GetPcieSlotConfigProtocol0** |  |
|  | **GetPcieSlotTable1** |  |
|  | **GetPcieSlotTable2** |  |
|  | **SetPcieSlotNumberCallback** |  |
|  | **_ModuleEntryPoint** |  |
| Global | **variables - cached UEFI system table pointers and protocol interfaces.** |  |
| Initialized | **by _ModuleEntryPoint.** |  |
| EFI_HANDLE | **gImageHandle     = NULL; ///< @ 0xF20: Image handle from DXE dispatcher** |  |
| Protocol | **GUIDs and configuration data (defined in .rdata section).** |  |
| Forward | **declarations of internal functions** |  |
| VOID | ***EFIAPI GetHobList        (VOID);** |  |
| SystemTable | **is at a fixed offset from gST.** |  |
| gST | **+ 0x68 (104) = NumberOfTableEntries** |  |
| gST | **+ 0x70 (112) = ConfigurationTable pointer** |  |
| EntryCount | **= *(UINTN *)((UINT8 *)gST + 104);** |  |
| Each | **config table entry: 16-byte GUID + 8-byte pointer (24 bytes total)** |  |
| if | **(IsGuidEqual (** |  |
| PoolSize | **= (UINTN)gBS->AllocatePool (31);** |  |
| if | **(gBS->LocateProtocol (&gDebugLibProtocolGuid, NULL, &gDebugProtocol) < 0) {** |  |
| Read | **current CMOS index, preserving NMI enable bit** |  |
| CmosNmiSave | **= __inbyte (0x70);** |  |
| Read | **debug level from CMOS register 0x4B** |  |
| DebugLevel | **= __inbyte (0x71);** |  |
| Bit | **1 indicates debug capability** |  |
| DebugLevel | **= (*(volatile UINT8 *)0xFDAF0490) & 2 | 1;** |  |
| Convert | **level 1..4 into ErrorLevel mask** |  |
| if | **(DebugLevel - 1 <= 0xFD) {** |  |
| EFI_D_ERROR | **} else {** |  |
| Check | **mask match and call DebugPrint if it matches** |  |
| if | **((ErrorLevel & 0x80000000) != 0) {** |  |
| Callback | **0: PcieSlotChecker** |  |
| This | **slot bit is not set - skip** |  |
| Bitmap | **= SlotBitmap;** |  |
| Open | **PCI Root Bridge I/O Protocol for PCI config access** |  |
| Build | **config address: ((Bus | ((Device | (Function << 8)) << 8)) << 8)** |  |
| ConfigBase | **= (Entry->Bus | ((Entry->Device | (Entry->Function << 8)) << 8)) << 8;** |  |
| Read | **PCI config register at offset 0x19 (sub-class code)** |  |
| Read | **PCI config register at offset 0x1A (base class code)** |  |
| Check | **if PcieAddress is in range [ConfigByte1, ConfigByte2]** |  |
| InRange | **= FALSE;** |  |
| Callback | **1: GetPcieSlotConfigProtocol0** |  |
| Callback | **2: GetPcieSlotTable1** |  |
| Callback | **3: GetPcieSlotTable2** |  |
| Callback | **4: SetPcieSlotNumberCallback** |  |
| Entry | **Point: _ModuleEntryPoint** |  |
| Save | **image handle (assert if NULL)** |  |
| gImageHandle | **= (UINT64)ImageHandle;** |  |
| Save | **system table (assert if NULL)** |  |
| gST | **= (UINT64)SystemTable;** |  |
| Save | **boot services (assert if NULL)** |  |
| gBS | **= (UINT64)SystemTable->BootServices;** |  |
| Save | **runtime services (assert if NULL)** |  |
| gRT | **= (UINT64)SystemTable->RuntimeServices;** |  |
| Locate | **HOB list** |  |
| GetHobList | **();** |  |
| Log | **driver type** |  |
| DebugPrint | **(0x80000000, "UBA:OpromUpdate-TypeNeonCityFPGA\n");** |  |
| Locate | **UBA board-type protocol** |  |
| BoardProtocol | **= NULL;** |  |
| Register | **OpROM update config: 5 callback functions + GUID + 48 bytes config** |  |
| if | **(!EFI_ERROR (Status)) {** |  |

---
*Generated by HR650X BIOS Decompilation Project*