/** @file
  OpromUpdateDxeCLX64L.h -- Header for OpromUpdateDxeCLX64L

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __OPROMUPDATEDXECLX64L_H__
#define __OPROMUPDATEDXECLX64L_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
UbaDebugPrint(
  VOID
);

EFI_STATUS
EFIAPI
SetPcieSlotNumber(
  VOID
);

EFI_STATUS
EFIAPI
GetPcieSlotNumber(
  VOID
);

EFI_STATUS
EFIAPI
GetBusScanLimit(
  VOID
);

EFI_STATUS
EFIAPI
GetBusScanLimit2(
  VOID
);

EFI_STATUS
EFIAPI
SetPcieSlotCallback(
  VOID
);

EFI_STATUS
EFIAPI
ReadUnaligned64(
  VOID
);

EFI_STATUS
EFIAPI
IsGuidMatch(
  VOID
);

EFI_STATUS
EFIAPI
UefiMain(
  VOID
);

EFI_STATUS
EFIAPI
data(
  VOID
);

EFI_STATUS
EFIAPI
gImageHandle     = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
used by this driver:(
  VOID
);

EFI_STATUS
EFIAPI
- protocol for PCI root bridge I/O(
  VOID
);

EFI_STATUS
EFIAPI
- HOB list identifier(
  VOID
);

EFI_STATUS
EFIAPI
- variable architecture protocol(
  VOID
);

EFI_STATUS
EFIAPI
- ACPI support protocol(
  VOID
);

EFI_STATUS
EFIAPI
are referenced via the UBA configuration tables below.(
  VOID
);

EFI_STATUS
EFIAPI
gEfiPciRootBridgeIoProtocolGuid  = {0x2F707EBB, 0x4A1A, 0x11D4, {0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}};(
  VOID
);

EFI_STATUS
EFIAPI
Scan Limit Tables(
  VOID
);

EFI_STATUS
EFIAPI
tables define the PCIe devices on the CLX64L platform whose secondary(
  VOID
);

EFI_STATUS
EFIAPI
range is constrained for PCI enumeration. Each entry identifies a device(
  VOID
);

EFI_STATUS
EFIAPI
Segment/Bus/Device/Function and VendorId/DeviceId, and specifies the(
  VOID
);

EFI_STATUS
EFIAPI
primary and secondary bus limits.(
  VOID
);

EFI_STATUS
EFIAPI
1: Primary bus scan limits (6 entries).(
  VOID
);

EFI_STATUS
EFIAPI
on-board PCIe devices for CLX64L.(
  VOID
);

EFI_STATUS
EFIAPI
mBusScanLimitTable[] = {(
  VOID
);

EFI_STATUS
EFIAPI
0: 8086:1528 (Intel I350 PCIe Controller) at Bus 1, Dev 2, Func 0(
  VOID
);

EFI_STATUS
EFIAPI
0x02, BaseClass 0x02 (Network Controller)(
  VOID
);

EFI_STATUS
EFIAPI
scan range: primary up to 0x2D, secondary up to 0x2C(
  VOID
);

EFI_STATUS
EFIAPI
0x01, BDF range [0, 0xFF] x [0x2E, 0x2F](
  VOID
);

EFI_STATUS
EFIAPI
1: 8086:1521 (Intel I350 PCIe Controller) at Bus 1, Dev 1, Func 0(
  VOID
);

EFI_STATUS
EFIAPI
2: 8086:10FB (Intel X550/X557 10GbE Controller) at wildcard BDF(
  VOID
);

EFI_STATUS
EFIAPI
wildcard bus range(
  VOID
);

EFI_STATUS
EFIAPI
3: 8086:1521 at Dev 4, Func 4 (second instance)(
  VOID
);

EFI_STATUS
EFIAPI
0x04, BDF range [0, 0xFF] x [0x2E, 0x2F](
  VOID
);

EFI_STATUS
EFIAPI
4: 8086:1528 at Dev 2, Func 9 (third instance)(
  VOID
);

EFI_STATUS
EFIAPI
scan range wildcard(
  VOID
);

EFI_STATUS
EFIAPI
5: Additional device at Bus 2, Dev 16, Func 3(
  VOID
);

EFI_STATUS
EFIAPI
0x15B3 (Mellanox), Device 0x1003(
  VOID
);

EFI_STATUS
EFIAPI
0x02 (Network Controller)(
  VOID
);

EFI_STATUS
EFIAPI
scan range: secondary up to 0x06(
  VOID
);

EFI_STATUS
EFIAPI
2: Secondary bus scan limits (not populated for CLX64L).(
  VOID
);

EFI_STATUS
EFIAPI
mBusScanLimitTable2[10] = { 0 };(
  VOID
);

EFI_STATUS
EFIAPI
Slot Mapping Table (CLX64L)(
  VOID
);

EFI_STATUS
EFIAPI
physical PCIe Root Port (Bus/Device/Function) to logical slot numbers.(
  VOID
);

EFI_STATUS
EFIAPI
entries correspond to the 8 PCIe root ports on the CLX64L platform.(
  VOID
);

EFI_STATUS
EFIAPI
for slot bit i. The slot number in byte 3 is 0 for all entries since(
  VOID
);

EFI_STATUS
EFIAPI
numbering is derived from the bit position (not an explicit number).(
  VOID
);

EFI_STATUS
EFIAPI
mSlotMappingTable[] = {(
  VOID
);

EFI_STATUS
EFIAPI
0: Bus 0, Dev 3,  Func 0(
  VOID
);

EFI_STATUS
EFIAPI
1: Bus 80h, Dev 1, Func 0 (PCH)(
  VOID
);

EFI_STATUS
EFIAPI
2: Bus 80h, Dev 2, Func 0 (PCH)(
  VOID
);

EFI_STATUS
EFIAPI
3: Bus 80h, Dev 3, Func 2 (PCH)(
  VOID
);

EFI_STATUS
EFIAPI
4: Bus 0,  Dev 2, Func 0(
  VOID
);

EFI_STATUS
EFIAPI
5: Bus 0,  Dev 1, Func 0(
  VOID
);

EFI_STATUS
EFIAPI
6: Bus 0,  Dev 1Ch, Func 5(
  VOID
);

EFI_STATUS
EFIAPI
7: Bus 80h, Dev 3, Func 0 (PCH)(
  VOID
);

EFI_STATUS
EFIAPI
protocol instance. Registered with the UBA framework during(
  VOID
);

EFI_STATUS
EFIAPI
to provide CLX64L-specific OpROM update callbacks.(
  VOID
);

EFI_STATUS
EFIAPI
mUbaOpromUpdateProtocol = {(
  VOID
);

EFI_STATUS
EFIAPI
Debug Print(
  VOID
);

EFI_STATUS
EFIAPI
a debug message through the UBA protocol's debug channel.(
  VOID
);

EFI_STATUS
EFIAPI
UbaDebugPrint ((
  VOID
);

EFI_STATUS
EFIAPI
CMOS register 0x70 to check platform type(
  VOID
);

EFI_STATUS
EFIAPI
0x4B bit 7 = reserved, bits [1:0] = platform type(
  VOID
);

EFI_STATUS
EFIAPI
0 = unknown, Type 1 = CLX platform, Type 2-3 = other(
  VOID
);

EFI_STATUS
EFIAPI
= IoRead8 (0x70);(
  VOID
);

EFI_STATUS
EFIAPI
type is valid (not -1/0xFF)(
  VOID
);

EFI_STATUS
EFIAPI
(DebugLevel & 0x80000000) {(
  VOID
);

EFI_STATUS
EFIAPI
platform: write through debug function(
  VOID
);

EFI_STATUS
EFIAPI
(Marker, Format);(
  VOID
);

EFI_STATUS
EFIAPI
through registered UBA debug function (offset 0 in protocol)(
  VOID
);

EFI_STATUS
EFIAPI
//(
  VOID
);

EFI_STATUS
EFIAPI
whether a given Bus/Device/Function is within the valid slot(
  VOID
);

EFI_STATUS
EFIAPI
for the specified slot bitmask on CLX64L.(
  VOID
);

EFI_STATUS
EFIAPI
each slot bit set in SlotMask, this function retrieves the PCI root(
  VOID
);

EFI_STATUS
EFIAPI
protocol, reads the bridge's bus number range (via(
  VOID
);

EFI_STATUS
EFIAPI
with PCI attributes 0x19 and 0x1A), and checks whether(
  VOID
);

EFI_STATUS
EFIAPI
falls within that range.(
  VOID
);

EFI_STATUS
EFIAPI
EFIAPI(
  VOID
);

EFI_STATUS
EFIAPI
slot is not enabled in the bitmask; skip it.(
  VOID
);

EFI_STATUS
EFIAPI
+= sizeof (UBA_OPROM_SLOT_MAPPING);(
  VOID
);

EFI_STATUS
EFIAPI
the PCI Root Bridge I/O protocol for this root port.(
  VOID
);

EFI_STATUS
EFIAPI
= gBootServices->LocateProtocol ((
  VOID
);

EFI_STATUS
EFIAPI
the PCI address from slot mapping entry:(
  VOID
);

EFI_STATUS
EFIAPI
are packed into the "DeviceFunction" field used(
  VOID
);

EFI_STATUS
EFIAPI
PCI root bridge operations.(
  VOID
);

EFI_STATUS
EFIAPI
bus number range for this root port.(
  VOID
);

EFI_STATUS
EFIAPI
0x19 = Get primary bus number(
  VOID
);

EFI_STATUS
EFIAPI
0x1A = Get secondary bus number (subordinate)(
  VOID
);

EFI_STATUS
EFIAPI
a pointer to gEfiAcpiSupportProtocolGuid, which identifies the(
  VOID
);

EFI_STATUS
EFIAPI
support protocol used for slot number querying.(
  VOID
);

EFI_STATUS
EFIAPI
the primary bus scan limit table for CLX64L.(
  VOID
);

EFI_STATUS
EFIAPI
table defines which PCIe devices on this platform have restricted(
  VOID
);

EFI_STATUS
EFIAPI
ranges for enumeration.(
  VOID
);

EFI_STATUS
EFIAPI
the secondary bus scan limit table for CLX64L.(
  VOID
);

EFI_STATUS
EFIAPI
table is reserved and currently contains zero-initialized entries.(
  VOID
);

EFI_STATUS
EFIAPI
when a PCIe slot number assignment callback occurs.(
  VOID
);

EFI_STATUS
EFIAPI
function sets the slot value to 2 and logs the event.(
  VOID
);

EFI_STATUS
EFIAPI
the UBA protocol instance. On first call, searches the HOB list(
  VOID
);

EFI_STATUS
EFIAPI
the gEfiVariableArchProtocolGuid HOB and records the HOB data pointer.(
  VOID
);

EFI_STATUS
EFIAPI
GetUbaProtocol ((
  VOID
);

EFI_STATUS
EFIAPI
the HOB list for the Variable Arch protocol HOB.(
  VOID
);

EFI_STATUS
EFIAPI
HOB list is obtained from SystemTable->HobList.(
  VOID
);

EFI_STATUS
EFIAPI
= NULL;(
  VOID
);

EFI_STATUS
EFIAPI
entries are 24 bytes each(
  VOID
);

EFI_STATUS
EFIAPI
a 64-bit value from an unaligned address, with NULL pointer assertion.(
  VOID
);

EFI_STATUS
EFIAPI
ReadUnaligned64 ((
  VOID
);

EFI_STATUS
EFIAPI
two GUID values as a pair of 64-bit quantities.(
  VOID
);

EFI_STATUS
EFIAPI
IsGuidMatch ((
  VOID
);

EFI_STATUS
EFIAPI
the HOB (Hand-Off Block) list pointer by searching the system(
  VOID
);

EFI_STATUS
EFIAPI
table for the gEfiHobListGuid entry.(
  VOID
);

EFI_STATUS
EFIAPI
first call, scans the configuration table, validates the retrieved HOB(
  VOID
);

EFI_STATUS
EFIAPI
*(
  VOID
);

EFI_STATUS
EFIAPI
HOB list physical address is stored in the first configuration table(
  VOID
);

EFI_STATUS
EFIAPI
if the table reports at least 16 entries (EfiMemoryMap).(
  VOID
);

EFI_STATUS
EFIAPI
(gBootServices == NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
base must be > 16 to be valid (below 16 is ISA/memory reserved).(
  VOID
);

EFI_STATUS
EFIAPI
(also UefiMain)(
  VOID
);

EFI_STATUS
EFIAPI
driver entry point for OpromUpdateDxeCLX64L.(
  VOID
);

EFI_STATUS
EFIAPI
global service pointers (ImageHandle, SystemTable, BootServices(
  VOID
);

EFI_STATUS
EFIAPI
OpromUpdate configuration with the UBA framework.(
  VOID
);

EFI_STATUS
EFIAPI
UBA configuration includes:(
  VOID
);

EFI_STATUS
EFIAPI
UEFI global pointers for library functions.(
  VOID
);

EFI_STATUS
EFIAPI
= ImageHandle;(
  VOID
);

EFI_STATUS
EFIAPI
the HOB list.(
  VOID
);

EFI_STATUS
EFIAPI
();(
  VOID
);

EFI_STATUS
EFIAPI
the UBA OpromUpdate registration for CLX64L.(
  VOID
);

EFI_STATUS
EFIAPI
(UBA_DEBUG_LEVEL, "UBA:OpromUpdate-TypeClx64L\n");(
  VOID
);

EFI_STATUS
EFIAPI
the PCI Root Bridge I/O protocol and install the UBA(
  VOID
);

EFI_STATUS
EFIAPI
configuration table.(
  VOID
);

EFI_STATUS
EFIAPI
= &mUbaOpromUpdateProtocol;(
  VOID
);

EFI_STATUS
EFIAPI
the UBA configuration with the root bridge driver.(
  VOID
);

EFI_STATUS
EFIAPI
configuration includes the slot mapping table, bus scan limits(
  VOID
);

EFI_STATUS
EFIAPI
callback functions.(
  VOID
);

EFI_STATUS
EFIAPI
= RootBridgeIo->SetAttributes ((
  VOID
);

EFI_STATUS
EFIAPI
default configuration(
  VOID
);

EFI_STATUS
EFIAPI
of UBA configuration structure(
  VOID
);

#endif /* __OPROMUPDATEDXECLX64L_H__ */