# OpromUpdateDxeCLX64L

## Function Table

| Address | Name | Description |
|---------|------|-------------|
|  | **UbaDebugPrint** |  |
|  | **SetPcieSlotNumber** |  |
|  | **GetPcieSlotNumber** |  |
|  | **GetBusScanLimit** |  |
|  | **GetBusScanLimit2** |  |
|  | **SetPcieSlotCallback** |  |
|  | **ReadUnaligned64** |  |
|  | **IsGuidMatch** |  |
|  | **UefiMain** |  |
| Global | **data** |  |
| EFI_HANDLE | **gImageHandle     = NULL;** |  |
| GUIDs | **used by this driver:** |  |
| gEfiPciRootBridgeIoProtocolGuid | **- protocol for PCI root bridge I/O** |  |
| gEfiHobListGuid | **- HOB list identifier** |  |
| gEfiVariableArchProtocolGuid | **- variable architecture protocol** |  |
| gEfiAcpiSupportProtocolGuid | **- ACPI support protocol** |  |
| These | **are referenced via the UBA configuration tables below.** |  |
| EFI_GUID | **gEfiPciRootBridgeIoProtocolGuid  = {0x2F707EBB, 0x4A1A, 0x11D4, {0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}};** |  |
| Bus | **Scan Limit Tables** |  |
| These | **tables define the PCIe devices on the CLX64L platform whose secondary** |  |
| bus | **range is constrained for PCI enumeration. Each entry identifies a device** |  |
| by | **Segment/Bus/Device/Function and VendorId/DeviceId, and specifies the** |  |
| allowed | **primary and secondary bus limits.** |  |
| Table | **1: Primary bus scan limits (6 entries).** |  |
| Covers | **on-board PCIe devices for CLX64L.** |  |
| UBA_OPROM_BUS_SCAN_LIMIT_ENTRY | **mBusScanLimitTable[] = {** |  |
| Entry | **0: 8086:1528 (Intel I350 PCIe Controller) at Bus 1, Dev 2, Func 0** |  |
| Rev | **0x02, BaseClass 0x02 (Network Controller)** |  |
| Bus | **scan range: primary up to 0x2D, secondary up to 0x2C** |  |
| Slot | **0x01, BDF range [0, 0xFF] x [0x2E, 0x2F]** |  |
| Entry | **1: 8086:1521 (Intel I350 PCIe Controller) at Bus 1, Dev 1, Func 0** |  |
| Entry | **2: 8086:10FB (Intel X550/X557 10GbE Controller) at wildcard BDF** |  |
| Broad | **wildcard bus range** |  |
| Entry | **3: 8086:1521 at Dev 4, Func 4 (second instance)** |  |
| Slot | **0x04, BDF range [0, 0xFF] x [0x2E, 0x2F]** |  |
| Entry | **4: 8086:1528 at Dev 2, Func 9 (third instance)** |  |
| Bus | **scan range wildcard** |  |
| Entry | **5: Additional device at Bus 2, Dev 16, Func 3** |  |
| Vendor | **0x15B3 (Mellanox), Device 0x1003** |  |
| BaseClass | **0x02 (Network Controller)** |  |
| Bus | **scan range: secondary up to 0x06** |  |
| Table | **2: Secondary bus scan limits (not populated for CLX64L).** |  |
| UBA_OPROM_BUS_SCAN_LIMIT_ENTRY | **mBusScanLimitTable2[10] = { 0 };** |  |
| PCIe | **Slot Mapping Table (CLX64L)** |  |
| Maps | **physical PCIe Root Port (Bus/Device/Function) to logical slot numbers.** |  |
| 8 | **entries correspond to the 8 PCIe root ports on the CLX64L platform.** |  |
| BDF | **for slot bit i. The slot number in byte 3 is 0 for all entries since** |  |
| slot | **numbering is derived from the bit position (not an explicit number).** |  |
| UBA_OPROM_SLOT_MAPPING | **mSlotMappingTable[] = {** |  |
| Slot | **0: Bus 0, Dev 3,  Func 0** |  |
| Slot | **1: Bus 80h, Dev 1, Func 0 (PCH)** |  |
| Slot | **2: Bus 80h, Dev 2, Func 0 (PCH)** |  |
| Slot | **3: Bus 80h, Dev 3, Func 2 (PCH)** |  |
| Slot | **4: Bus 0,  Dev 2, Func 0** |  |
| Slot | **5: Bus 0,  Dev 1, Func 0** |  |
| Slot | **6: Bus 0,  Dev 1Ch, Func 5** |  |
| Slot | **7: Bus 80h, Dev 3, Func 0 (PCH)** |  |
| UBA | **protocol instance. Registered with the UBA framework during** |  |
| ModuleEntryPoint | **to provide CLX64L-specific OpROM update callbacks.** |  |
| UBA_OPROM_UPDATE_PROTOCOL | **mUbaOpromUpdateProtocol = {** |  |
| UBA | **Debug Print** |  |
| Writes | **a debug message through the UBA protocol's debug channel.** |  |
| VOID | **UbaDebugPrint (** |  |
| Read | **CMOS register 0x70 to check platform type** |  |
| CMOS | **0x4B bit 7 = reserved, bits [1:0] = platform type** |  |
| Type | **0 = unknown, Type 1 = CLX platform, Type 2-3 = other** |  |
| CmosValue | **= IoRead8 (0x70);** |  |
| Platform | **type is valid (not -1/0xFF)** |  |
| if | **(DebugLevel & 0x80000000) {** |  |
| CLX | **platform: write through debug function** |  |
| VA_START | **(Marker, Format);** |  |
| Output | **through registered UBA debug function (offset 0 in protocol)** |  |
| SetPcieSlotNumber | **//** |  |
| Determines | **whether a given Bus/Device/Function is within the valid slot** |  |
| range | **for the specified slot bitmask on CLX64L.** |  |
| For | **each slot bit set in SlotMask, this function retrieves the PCI root** |  |
| bridge | **protocol, reads the bridge's bus number range (via** |  |
| SetAttributes | **with PCI attributes 0x19 and 0x1A), and checks whether** |  |
| BusDeviceFunction | **falls within that range.** |  |
| BOOLEAN | **EFIAPI** |  |
| This | **slot is not enabled in the bitmask; skip it.** |  |
| SlotEntry | **+= sizeof (UBA_OPROM_SLOT_MAPPING);** |  |
| Locate | **the PCI Root Bridge I/O protocol for this root port.** |  |
| Status | **= gBootServices->LocateProtocol (** |  |
| Build | **the PCI address from slot mapping entry:** |  |
| These | **are packed into the "DeviceFunction" field used** |  |
| for | **PCI root bridge operations.** |  |
| Get | **bus number range for this root port.** |  |
| Attribute | **0x19 = Get primary bus number** |  |
| Attribute | **0x1A = Get secondary bus number (subordinate)** |  |
| Returns | **a pointer to gEfiAcpiSupportProtocolGuid, which identifies the** |  |
| ACPI | **support protocol used for slot number querying.** |  |
| Returns | **the primary bus scan limit table for CLX64L.** |  |
| The | **table defines which PCIe devices on this platform have restricted** |  |
| bus | **ranges for enumeration.** |  |
| Returns | **the secondary bus scan limit table for CLX64L.** |  |
| This | **table is reserved and currently contains zero-initialized entries.** |  |
| Called | **when a PCIe slot number assignment callback occurs.** |  |
| This | **function sets the slot value to 2 and logs the event.** |  |
| Retrieves | **the UBA protocol instance. On first call, searches the HOB list** |  |
| for | **the gEfiVariableArchProtocolGuid HOB and records the HOB data pointer.** |  |
| EFI_HANDLE | **GetUbaProtocol (** |  |
| Search | **the HOB list for the Variable Arch protocol HOB.** |  |
| The | **HOB list is obtained from SystemTable->HobList.** |  |
| Handle | **= NULL;** |  |
| ConfigurationTable | **entries are 24 bytes each** |  |
| Reads | **a 64-bit value from an unaligned address, with NULL pointer assertion.** |  |
| UINT64 | **ReadUnaligned64 (** |  |
| Compares | **two GUID values as a pair of 64-bit quantities.** |  |
| BOOLEAN | **IsGuidMatch (** |  |
| Retrieves | **the HOB (Hand-Off Block) list pointer by searching the system** |  |
| configuration | **table for the gEfiHobListGuid entry.** |  |
| On | **first call, scans the configuration table, validates the retrieved HOB** |  |
| VOID | ***** |  |
| The | **HOB list physical address is stored in the first configuration table** |  |
| entry | **if the table reports at least 16 entries (EfiMemoryMap).** |  |
| if | **(gBootServices == NULL) {** |  |
| Memory | **base must be > 16 to be valid (below 16 is ISA/memory reserved).** |  |
| ModuleEntryPoint | **(also UefiMain)** |  |
| UEFI | **driver entry point for OpromUpdateDxeCLX64L.** |  |
| Initializes | **global service pointers (ImageHandle, SystemTable, BootServices** |  |
| UBA | **OpromUpdate configuration with the UBA framework.** |  |
| The | **UBA configuration includes:** |  |
| Save | **UEFI global pointers for library functions.** |  |
| gImageHandle | **= ImageHandle;** |  |
| Initialize | **the HOB list.** |  |
| GetHobList | **();** |  |
| Log | **the UBA OpromUpdate registration for CLX64L.** |  |
| UbaDebugPrint | **(UBA_DEBUG_LEVEL, "UBA:OpromUpdate-TypeClx64L\n");** |  |
| Locate | **the PCI Root Bridge I/O protocol and install the UBA** |  |
| OpromUpdate | **configuration table.** |  |
| ConfigTable | **= &mUbaOpromUpdateProtocol;** |  |
| Register | **the UBA configuration with the root bridge driver.** |  |
| The | **configuration includes the slot mapping table, bus scan limits** |  |
| and | **callback functions.** |  |
| Status | **= RootBridgeIo->SetAttributes (** |  |
| Use | **default configuration** |  |
| Size | **of UBA configuration structure** |  |

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*Generated by HR650X BIOS Decompilation Project*