OemErrorLogDxe

Function Table

Address	Name	Description
	CpuId
	ReadUnaligned64Wrapper
	CompareGuidByQwords
	FreePoolChecked
	DebugAssertWorker
	DebugPrintWrapper
	DebugPrintCmosAware
	LocateIpmiTransport
	GetBmcLogBus
	ApCollectCpuInfo
	OemCheckCpuInfoNotify
	OemErrorLogDxeLibConstructor
	OemErrorLogDxeEntryPoint
EFI	global protocol/table pointers
EFI_HANDLE	gImageHandle = NULL;
Module	globals
EFI_MP_SERVICES_PROTOCOL	*gMpService = NULL; // qword_1698
qword_1690	*UINT32 gSteppingValues = NULL; // qword_1688**
qword_1680	*VOID gHobList = NULL; // qword_16C8**
qword_16D0	*VOID gDebugPrintProtocol = NULL; // qword_16C0**
n3	at 0x16D8
GUID	definitions (from .data section at 0x1640)
gEfiMpServiceProtocolGuid	= { 3FDDA605-A76E-4F46-AD29-12F4531B3D08 }
GUID	at 0x1650 = { 36232936-0E76-31C8-A13A-3AF2FC1C3932 } (EFI_HOB_LIST_GUID)
GUID	at 0x1660 (unk_1660) = { 4A1D0E66-5271-4E22-83FE-90921B748213 } (gEfiIpmiTransportGuid)
Check	if running in SMM or similar restricted context (< 0x10 pages free)
if	(gBootServices->GetBootMode () == BOOT_ON_S3_RESUME) {
Read	current debug level from CMOS
IoWrite8	**(0x70, (IoRead8 (0x70) & 0x80)	0x4B);**
DebugLevel	= ((volatile UINT8 )(UINTN)0xFDAF0490) & 2	1;**
gEfiHobListGuid	))
gEfiIpmiTransportProtocolGuid	NULL
IPMI	command data structures for CPU mismatch SEL
0x20	= BIOS
0x04	UINT8 SensorType; // 0x02 = Processor
0x72	**UINT8 EventDirType; // Event Dir (bit 7)	Event Type**
0x6F	= OEM specific / Sensor-specific offset
0x44	= OEM byte
Send	IPMI command 0x2E (0x46, 0x01) to IPMI transport
IpmiCmd	= NULL; // command data: {0x02}, length 1
NetFn	0, // LUN
Command	*(UINT8 )IpmiCmd**
Request	length
VarData	= NULL;
Setup	variable GUID
Offset	284 in Setup variable = BMC bus
Get	current processor number from MP services
Read	microcode version from MSR 0x8B
AsmWriteMsr64	(0x8B, 0);
Read	stepping from CPUID (EAX[3:0] after CPUID leaf 1)
if	(gSteppingValues != NULL) {
Read	frequency from MSR 0xCE (Platform Info MSR)
if	(gFrequencies != NULL) {
Byte	1 of MSR 0xCE contains the max non-turbo ratio in 100 MHz units
Status	= gBootServices->LocateProtocol (
placeholder	for watchdog timer
gMicrocodeVersions	= AllocatePoolOrNull (BufferSize);
ApCollectCpuInfo	(NULL);
SingleThread	NULL, // WaitEvent
TimeoutInMicroseconds	(infinite)
ProcedureArgument	NULL // FailedCpuList
MicrocodeMismatch	= FALSE;
if	(gMicrocodeVersions != NULL) {
if	**(MicrocodeMismatch		FrequencyMismatch	SteppingMismatch) {**
Determine	BMC bus for SEL
Status	= GetBmcLogBus (&BusValue);
Build	IPMI SEL record
BIOS	SelRecord.EvMRevision = 0x04;
Processor	SelRecord.SensorNumber = 0x72;
Event	**Dir	Event Type**
OEM	specific
bit	4: microcode
bit	0: frequency
bit	3: stepping
OEM	byte
Send	IPMI command (NetFn=0x0A, Cmd=0x44) to add SEL entry
ResponseSize	= sizeof (ResponseData);
LUN	0x44, // Command: Add SEL Entry
Save	global pointers
gImageHandle	= ImageHandle;
Initialize	HOB list
GetHobList	();
Locate	IPMI transport protocol to prepare for SEL logging
IPMI	not available yet; register for protocol notification
Status	= gBootServices->RegisterProtocolNotify (
gEfiIpmiTransportProtocolGuid	(EFI_EVENT)(UINTN)LocateIpmiTransport
Initialize	UEFI globals and construct library
Status	= OemErrorLogDxeLibConstructor (ImageHandle, SystemTable);
Register	the CPU check notification via MP services protocol notify
Check	immediately after registration for already-present protocol
OemCheckCpuInfoNotify	(NULL, NULL);

Generated by HR650X BIOS Decompilation Project