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PchInitDxe

Index: 134 | Size: 87,652 bytes (15664h) | Phase: DXE

Overview

Primary PCH initialization DXE driver for the Intel Lewisburg (LBG) PCH on the Purley platform. This is one of the largest modules in the firmware, responsible for comprehensive PCH bring-up during the DXE phase including: PCIe Root Port (RP) ASPM/L1SS/ClkReq configuration, USB XHCI preconditioning (warm reset), SATA controller BAR/interrupt/power management setup, uplink port (x16/x8) programming, GPIO pad configuration via sideband (PCR) registers, ACPI NVS protocol installation, NHLT audio table publishing, TraceHub (MIPI) reveal, S3 boot script management, RST PCIe storage remapping, and P2SB/PMC configuration.

Key Functions

  • PchInitEntryPoint -- Main entry: consumes PCH policy HOB, initializes UEFI core globals, configures debug port, loads SATA RSTe option ROMs, triggers USB precondition, and registers EndOfDxe/ReadyToBoot/ExitBootServices callbacks
  • InitializePchDevice -- Hardware configuration loop covering PMC (SLP_S0), P2SB MMIO, GPIO PCR pads, SATA BARs/interrupts, and per-PCIe-RP ASPM/L1SS/ClkReq programming
  • PchUsbPrecondition -- XHCI warm reset workflow: locates XHCI PCI IO, enables MMIO/bus master, reads USB2 port counts from capability registers, sets up a timer-driven precondition context that programs USB ports
  • PchUplinksInit -- SKU-aware uplink port configuration: determines PCH SKU, programs Max Payload Size/Max Read Size for x16 (Device 0x37C0) or x8 (Device 0x37C1) uplinks and their downstream ports
  • InstallPchNvsProtocol -- Allocates 0x26D-byte ACPI NVS buffer, fills GPIO/SATA/PCIe/PCH SKU info, installs protocol for ASL consumption (patches NPCH name into DSDT)
  • PublishNhltAcpiTable -- Constructs and installs Non-HDAudio Link Table with endpoint descriptors from feature mask
  • PchInitS3BootScript -- Manages S3 boot script via SMM communication handlers registered at SmmReadyToLock

Protocols/Dependencies

  • PCI USRA protocol (MMIO config access)
  • PCH PCR sideband access (P2SB root port registers)
  • DXE Services Table, SMM Base2 Protocol, ACPI Table Protocol
  • PCD database: PCIe segment bus table, boot script pointer
  • PCH Policy HOB from PEI phase, EFI_GENERIC_VARIABLE for SMM communication

Platform

HR650X (Purley) -- Intel LBG PCH (Lewisburg), x86-64 PE32+ image