| Address | Name | Description |
|---|---|---|
| SioDeviceInit | ||
| PchPcrWriteReg | ||
| PchDetectSku | ||
| IsInterruptsEnabled | ||
| GetConfigTable | ||
| SioMmioBase | ||
| EnableInterrupts | ||
| DisableInterrupts | ||
| ReadEflags | ||
| IoRead16 | ||
| IoWrite16 | ||
| IoRead16Alt | ||
| IoWrite16Alt | ||
| IoRead32 | ||
| IoWrite32 | ||
| PciRead32 | ||
| PciWrite32 | ||
| PciRead16 | ||
| PciWrite16 | ||
| DebugPrint | ||
| DebugAssert | ||
| ReadUnaligned64 | ||
| CompareGuid | ||
| DebugGetLevel | ||
| ConfigureLpcIoRange | ||
| SetLpcRegisterRaw | ||
| ConfigureLpcDecode | ||
| SioDxeInitPre | ||
| ModuleEntryPoint | ||
| SioDeviceRead | ||
| SioDeviceWrite | ||
| SioDeviceRegister | ||
| SioDriverBindingStart | ||
| Global | variable declarations | |
| UEFI | service table pointers (cached at driver startup) | |
| EFI_SYSTEM_TABLE | *gST; ///< offset 0x2658 | |
| Driver | instance handle installed protocols on | |
| EFI_HANDLE | mDriverHandle = NULL; ///< offset 0x2650 | |
| SIO | DXE Init protocol structure (installed as protocol interface) | |
| SIO_DXE_INIT_PROTOCOL | mSioDxeInitProtocol; ///< offset 0x2600 | |
| Cached | PCH SKU type (detected at runtime) | |
| 0 | = Unknown, 1 = LbgPch, 2 = LbgPchH, 3 = Unsupported | |
| UINT32 | mPchSkuType = 3; ///< offset 0x2644 | |
| Debug | library state (report status code protocol) | |
| VOID | *mDebugLib = NULL; ///< offset 0x2678 | |
| Forward | declarations of local helper functions | |
| Interrupt | control helpers | |
| sub_390 | -- Enable interrupts (STI) | |
| STATIC | VOID | |
| sub_3A0 | -- Disable interrupts (CLI) | |
| sub_3B0 | -- Read EFLAGS | |
| STATIC | UINTN | |
| sub_1AAC | -- Check if interrupts are enabled (EFLAGS.IF bit 9) | |
| STATIC | BOOLEAN | |
| sub_B9C | -- Read UINT16 from I/O port (word-aligned check) | |
| STATIC | UINT16 | |
| sub_BCC | -- Write UINT16 to I/O port (word-aligned check) | |
| sub_C0C | -- Read UINT16 from I/O port | |
| sub_C40 | -- Write UINT16 to I/O port | |
| sub_C80 | -- Read UINT32 from I/O port (dword-aligned check) | |
| STATIC | UINT32 | |
| sub_CB0 | -- Write UINT32 to I/O port (dword-aligned check) | |
| PCI | Configuration via CF8/CFC (legacy I/O method) | |
| sub_17F0 | -- Read DWORD from PCI config space via CF8/CFC | |
| sub_189C | -- Write DWORD to PCI config space via CF8/CFC | |
| sub_1668 | -- Read WORD from PCI config space via CF8/CFC | |
| sub_1724 | -- Write WORD to PCI config space via CF8/CFC | |
| sub_2E0 | -- Internal memory copy with overlap support | |
| STATIC | VOID * | |
| Overlapping | from above: copy backwards | |
| UINT8 | DstEnd = (UINT8 )Destination + Length - 1; | |
| UINTN | Count8 = Length >> 3; | |
| PCH | PCR (Private Config Register) Write | |
| sub_195C | -- Write to PCH PCR register (base 0xFDEF0000) | |
| Handles | byte, word, and dword accesses. | |
| sub_1A14 | -- Detect PCH SKU type from LPC device ID (PCR register) | |
| LbgPch | } else if ((LpcDevId + 0x5E40) >= 0x100 && | |
| LbgPchH | } else { | |
| Debug | Library | |
| sub_6C8 | -- Get the debug library instance (report status code protocol) | |
| sub_748 | -- Debug print with severity mask check | |
| sub_790 | -- ASSERT check with debug print | |
| DXE | Services Table Retrieval | |
| sub_7D0 | -- Locate a configuration table by GUID from the system table | |
| STATIC | EFI_STATUS | |
| sub_D40 | -- Read 8 bytes unaligned | |
| STATIC | UINT64 | |
| sub_E18 | -- Compare two GUIDs (two 64-bit compare) | |
| DXE | Services / HOB / Protocol retrieval helpers | |
| sub_8C4 | -- Get the HOB list pointer from the configuration table | |
| sub_E80 | -- Locate PCD protocol (lazy init) | |
| STATIC | PCD_PROTOCOL * | |
| sub_894 | -- Get SIO MMIO base via MM PCI USRA protocol | |
| Accesses | the LPC bridge (B0 D31 F0) to get the | |
| B0 | D31 F0 | |
| MMIO | PciAddress.RegisterOffset = 0; | |
| Debug | Level Filter (sub_CF0) | |
| sub_CF0 | -- Read the current debug level from CMOS (RTC register 0x4B) | |
| Returns | EFI_D_INFO, EFI_D_WARN, or 0. | |
| Read | CMOS index, set to debug register 0x4B | |
| CmosIndex | = __inbyte (0x70); | |
| Check | platform debug enable (0xFDAF0490 register bit 1) | |
| ExtendedDebugLevel | *= ((volatile UINT8 *)0xFDAF0490 & 2) | 1;** |
| Map | debug level to EFID mask values | |
| if | (DebugLevel == 1) { | |
| 0x00000004 | } | |
| LPC | I/O Cycle Decode Configuration (sub_1450 / sub_1038 / sub_F0C) | |
| sub_1450 | -- Configure a new LPC I/O range decode entry. | |
| Manages | the 4-entry I/O range decode table in SIO MMIO. | |
| Finds | an available slot or resizes an existing overlapping range. | |
| Check | existing ranges for overlap or empty slot | |
| for | (EntryIndex = 0; EntryIndex < 4; EntryIndex++) { | |
| Empty | slot found | create entry |
| IoRangeEntry | **= (IoBase & LPC_IO_PORT_ENTRY_BASE_MASK) | ** |
| Check | IoBase within range | |
| Overlap | detected | update existing range |
| sub_F0C | -- Set up a custom IO range entry when DeviceType == 0xFF. | |
| Handles | LPC IO decode for a specific I/O address. | |
| Called | by sub_1038 for raw register access configurations. | |
| Scan | LPC IO decode registers at the given Cf8 address | |
| to | find which slot matches the requested register. | |
| SlotBase | = Register; | |
| sub_1038 | -- Core LPC IO cycle decode configuration. | |
| Routes | legacy device I/O ranges through the PCH LPC bridge. | |
| UART | if (IoConfig != 0) { | |
| LPT | case 3: // GPIO | |
| KBC | IoWrite16 (SIO_CONFIG_PORT, SIO_UNLOCK_KEY); | |
| PMC | IoWrite16 (SIO_CONFIG_PORT, SIO_GLOBAL_LOCK); | |
| PME | break; | |
| Raw | register access | |
| SIO | Protocol Implementation (sub_948) | |
| sub_948 | -- Initialize a specific SIO device (AST2500 DxeInit path) | |
| Handles | device configuration based on type. | |
| Module | Entry Point (sub_45C + _ModuleEntryPoint) | |
| sub_45C | -- Driver entry-point initialization. | |
| Sets | up service table pointers, locates protocols | |
| configures | PCH LPC I/O decode range, and installs | |
| the | SIO protocol interface. | |
| Initialize | UEFI service table pointers | |
| gImageHandle | = ImageHandle; | |
| Locate | DXE Services Table | |
| Status | = GetConfigTable (&gEfiDxeServicesTableGuid, (VOID )&gDS);** | |
| Locate | MM PCI USRA protocol | |
| if | (mPciUsra == NULL) { | |
| Initialize | HOB list | |
| GetHobList | (); | |
| Get | PCD protocol and configure PCIe segment bus | |
| Install | SIO protocol interface | |
| Status | = gBS->InstallMultipleProtocolInterfaces ( | |
| UEFI | Module Entry Point (sub_3C0 -> _ModuleEntryPoint) | |
| _ModuleEntryPoint | (at 0x3C0) | |
| The | UEFI DXE driver entry point. | |
| Calls | SioDxeInitPre to initialize, then installs the SIO protocol. | |
| EFI_STATUS | EFIAPI | |
| Initialize | driver | |
| Status | = SioDxeInitPre (ImageHandle, SystemTable); | |
| Install | protocol interface | |
| BootServices | = gBS; | |
| SIO | Protocol: SIO Device Read (SioDeviceRead stub) | |
| SIO | Protocol: SIO Device Write (SioDeviceWrite stub) | |
| SIO | Protocol: SIO Device Register (SioDeviceRegister stub) | |
| Protocol | structure initialization | |
| GUID | definitions and protocol references | |
| SIO | Protocol GUID: {9D36F7EF-6078-4419-8C46-2BBDB0E0C7B3} | |
| EFI_GUID | gEfiGenericSioProtocolGuid = SIO_PROTOCOL_GUID; | |
| sub_680 | -- SIO Driver Binding protocol "Start" stub | |
| sub_680 | -- Driver binding Start() function. | |
| Verifies | controller handle and initializes SIO. | |
| Initialize | SIO protocol instance |
Generated by HR650X BIOS Decompilation Project