TpmNvmeSupport

Function Table

Address	Name	Description
	CpuPause
	ReadTsc
	EnableInterrupts
	DisableInterrupts
	ReadEflags
	DebugPrint
	AssertBreak
	GetPciExpressBaseAddress
	PciExpressLibAddress
	IoWrite16
	IoRead32
	ReadUnaligned64
	CompareGuid
	TpmNvmeSupportEntry
	TpmNvmeSupportDxeEntry
	CheckNvmeDevicePresence
	NvmeCheckTimerNotify
GUID	Definitions
EFI_GUID	gAmiTcgPpiVariableGuid = AMI_TCG_PPI_VARIABLE_GUID;
Global	Data
EFI	BIOS globals.
EFI_HANDLE	gImageHandle = NULL;
Debug	mode protocol interface (obtained via LocateProtocol).
VOID	*gDebugModeProtocol = NULL;
HOB	list pointer cached from the system configuration table.
VOID	*gHobList = NULL;
PCI	Express base address from PCD token 5.
UINT64	gPciExpressBaseAddress = 0;
PCD	protocol interface (obtained via LocateProtocol).
VOID	*gPcdProtocol = NULL;
Helper	/ CPU Intrinsic Functions
Protocol	Access Helpers
Check	available memory	in very early phases this will be small.
MemorySize	= gBootServices->AllocatePages (AllocateAnyPages, EfiBootServicesData, 31);
DXE	phase	attempt to locate the debug protocol.
if	(gBootServices->LocateProtocol (
Debug	Print and Assert Support
Read	the CMOS debug level register.
CmosIndex	= IoRead8 (0x70) & 0x80;
Decode	the CMOS value to get the debug filter mask.
if	(CmosValue > 3) {
Read	hardware debug pin status.
DebugLevel	**= (MmioRead8 (0xFEDAF0490) & 2)	1;**
If	the message passes the filter, call the debug protocol print function.
if	((FilterMask & ErrorLevel) != 0) {
HOB	and PCD Access
Token	5 in the PCD database corresponds to PcdPciExpressBaseAddress.
gPciExpressBaseAddress	= PcdProtocol->Get5 (PcdToken (PcdPciExpressBaseAddress));
Core	Driver Logic
Save	the driver image handle.
gImageHandle	= ImageHandle;
Save	the system table.
gSystemTable	= SystemTable;
Save	the boot services table.
gBootServices	= SystemTable->BootServices;
Save	the runtime services table.
gRuntimeServices	= SystemTable->RuntimeServices;
Locate	the HOB list.
GetHobList	();
Obtain	the PCI Express base address from PCD.
If	the PcdPciExpressBaseAddress token is non-negative, enable
PCI	Express MMIO access by writing the port 0xCF8 command.
if	((INT8)PciExpressLibAddress (0xF0004) >= 0) {
Save	the current interrupt state and disable interrupts.
InterruptsOn	= (ReadEflags () & EFI_FLAGS_IF) != 0;
sufficient	for I/O posting to complete).
StartTsc	= (UINTN)IoRead32 (1288);
Restore	the interrupt state.
if	(InterruptsOn) {
Print	the module banner.
DEBUG	((DEBUG_INFO, " \n TpmNvmeSupportDxeEntry \n "));
Read	the AMI Setup variable to check if TPM NVMe support is enabled.
SetupVarSize	= sizeof (SetupData);
Field	at offset 0x12C (300) in the Setup structure holds the
TpmNvmeSupport	option	a single byte: 0x01 = enabled.
TpmNvmeSupportEnabled	= SetupData[300];
Clear	the AMI TCG PPI variable.
Delete	the AMITCGPPIVAR variable.
VarSize	= 0;
Perform	the initial NVMe device presence check.
Status	= CheckNvmeDevicePresence ();
Device	not found yet	register a periodic timer to retry.
Status	= gBootServices->SetTimer (
Locate	all handles that support the NVMe storage protocol.
Status	= gBootServices->LocateHandleBuffer (
Scan	all NVMe protocol handles for a live device.
Found	a responsive NVMe device.
NvmePresent	= 1;
Write	the presence flag into the AMI Setup variable.
Update	byte offset 300 in the Setup data (TpmNvmeSupport presence flag).
Retry	the NVMe device presence check.
Signal	the event to indicate completion.

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