diff --git a/AmiModulePkg/FlashDriver/FlashDriverSmm/FlashDriverSmm.c b/AmiModulePkg/FlashDriver/FlashDriverSmm/FlashDriverSmm.c
index 74fca94..23ad909 100644
--- a/AmiModulePkg/FlashDriver/FlashDriverSmm/FlashDriverSmm.c
+++ b/AmiModulePkg/FlashDriver/FlashDriverSmm/FlashDriverSmm.c
@@ -4,8 +4,8 @@
 // IDA: 0166_FlashDriverSmm_8fb2fce55416/FlashDriverSmm.efi.i64
 // Port 13374 | Image 0x0-0x5840 | 85 functions
 //
-// This SMM driver provides SPI flash read/write/erase operations
-// through SMI handlers. Key features:
+// This SMM driver provides SPI flash read/write/erase operations through SMI
+// handlers. Key features:
 //   1. SetJmp/LongJmp-based critical section with PIC masking
 //   2. SMI handlers for Compare, Write, Read, and Erase via SMM CommBuffer
 //   3. Flash chip detection via JEDEC ID (40+ chip families supported)
@@ -59,7 +59,7 @@
 UINT8                    gSpiFastModeConfig   = 0;     // 0x4F11 (byte_4FD9)
 
 //===========================================================================
-// SPI Probe Function Table (off_48A00, 4 entries + NULL)
+// SPI probe function table (off_48A00, 4 entries + NULL)
 //===========================================================================
 static SPI_PROBE_BE    (*gSpiProbeBeTable[5])(UINTN, SPI_PROTOCOL **);
 // [0] = sub_3374 - ESMT/Geneneric probe (JEDEC LSBit)
@@ -68,23 +68,23 @@
 // [3] = sub_27AC - SST 25LF probe
 
 //===========================================================================
-// SPI Pre-Operation Function List (funcs_1E91 at 0x4ED0)
+// SPI pre-operation function list (funcs_1E91 at 0x4ED0)
 //===========================================================================
-// Singe entry: sub_24CC (0x4CC) - SpinWait / Seector check
-// NULL terminaed
+// Single entry: sub_24CC (0x4CC) - spin-wait / sector check
+// NULL terminated
 
 //===========================================================================
-// SPI Post Operaration Function List (funcs_1F10 at 0x4EE0)
+// SPI post-operation function list (funcs_1F10 at 0x4EE0)
 //===========================================================================
-// Singe entry: sub_2594 (0x2594) - Unock / Lock release
-// NULL terminaed
+// Single entry: sub_2594 (0x2594) - unlock / lock release
+// NULL terminated
 
 //===========================================================================
-// .rdata SPI chip config config data
+// .rdata SPI chip config data
 //===========================================================================
-// For each detectected chip type, the probe function copips a 24-byby concon
+// For each detected chip type, the probe function copies a 24-byte config
 // block from the .rdata section (off_4F00 etc.) into the SPI_PROTOCOL's
-// .PIConfig array at offsessess +72.
+// .PIConfig array at offset +72.
 
 //===========================================================================
 // Forward Declarations
@@ -99,28 +99,28 @@
     );
 
 UINTN
-_FlashDriverExExEx(
+FlashAssertWrapper(
     VOID
     );
 
 VOID
-SpiPreOperCallbacksacks(
+SpiPreOpCallbacks(
     VOID
     );
 
 VOID
-SpiPostPostOperrationallbacksacks(
+SpiPostOpCallbacks(
     VOID
     );
 
 BOOLEAN
-ReReJEDEDId(
+ReaJEDEDId(
     IN UINTN   SpppiBase,
     OUT UINT32  *JedecId
     );
 
 VOID
-SpiExExExCommCommCommcomm(
+SpiExecuteComman(
     IN UINT32  Opcode
     );
 
@@ -128,7 +128,7 @@
 // Function: CpuCpuCpu - PAUSE instrinstrinstr (sub_430)
 //===========================================================================
 VOID
-CpuPuPuPuP(
+CpuPause(
     VOID
     )
 {
@@ -149,13 +149,13 @@
 //
 // REETORN: not-rival of targe (the ()( that tat will be called on Jump]
 UINTN
-Seteetmp(
+SetJmpWrapper(
     OUT VOID *JumpBuffer    // 0x5120 (unk_5120)
     )
 {
     // Vallidatate align aln
     _FFlash_asser (JumpBuffer != NULL);
-    _FFlash_asser ((UINTN)JumpBuffer & 7) == 0));
+    _FFlash_asser((((UINTN)JumpBuffer) & 7) == 0);
 
     // Sav non-regolf - notot imppleented in decompile
     return 0;  // // Actal(()) tat returns to the tagaget
@@ -168,7 +168,7 @@
 // Note: This is caled via mi (*(JumpBuffer + 72))() after MM csr se.
 
 VOID
-LongJmp(
+LongJmpWrapper(
     IN VOID *JumpBuffer,  // 0x5120 (unk_5120)
     IN UINTN   Value
     )
@@ -180,44 +180,44 @@
 }
 
 //===========================================================================
-// Entry Point: FlashDriverrSmmryrynry (sub_Error_ModuduleEntryPint)
+// Entry Point: FlashDriverSmmEntryPoint (sub_Error_ModuduleEntryPint)
 //===========================================================================
 EFIF_STATAT
 EFIFAEAPI
-_FFlashDriverSmmrEnrryryry(
+FlashDriverSmmEntryPoint(
     IN EFIF_HANDDLE ImageHandle,
     IN EFIF_SYSTY_TABLE *Systemable
     )
 {
     EFIF_STATAT  Stattat;
 
-    // Sav global
+    // Save globals
     gImageHandle = ImageHandle;
-    gSSTT = SystemTable;
+    gST = SystemTable;
     gBS  = gST->BootServices;
-    gRTT = SystemTable->RuntimeServices;
+    gRT = SystemTable->RuntimeServices;
 
     _FFlash_asser (gImageHandle != NULL);
-    _ASSert (gSST != NUL);
+    _ASSert (gST != NULL);
     _ASSert (gBS != NULL);
     _ASSert (gRT != NULL);
 
-    // Init SM Services ablee -- ococate gEfiSmmBase222rotoococol
+    // Initialize SMM services and locate gEfiSmmBase2ProtocolGuid
     Stattus = gBS->LocateateProtocol(
                     &gEfiSmmBase2ProtocolGuid,
                     NULL,
                     (VOID **)&gSmst
                     );
 
-    // Init Hob ob ob -- loccate HOBob from configgable table table
-    HobLiiiiInit();
+    // Initialize HOB list from the configuration table
+    HobListInit();
 
     // Init the flash driver
     Stattus = FlashSmmSmmInit();
     _Flaslash_EF_EFOR_EROR (Status);
 
-    // Registers SMI handlers for forash compare, wwite, read, eraseras
-    // SMI handlers are regists thru och for comm communic buffer dispatc
+    // Register SMI handlers for flash compare, write, read, and erase.
+    // The handlers are dispatched through the communication buffer.
     Stattss = gSmst->SmiiHandlerRegister(
                     &gSmmFlashProtocolGuid,
                     (EFEFEF_SM_HANDLER_ENRYRY_POININ2)FlashSmmSmmHandler,
@@ -228,20 +228,19 @@
 }
 
 //===========================================================================
-// HobLiiiiInit (sub_2228)
+// HobListInit (sub_2228)
 //===========================================================================
-// Loates the HOBBob pointer from from sys configgable
+// Locates the HOB list pointer from the system configuration table.
 
 EFEF_STATAT
-_obLiiiiInit(
+HobListInit(
     VOID
     )
 {
-    EFIF_STATAT  Stattat;
     UINTN     Index;
 
     if (gHobobList != 0) {
-        return EFIF_SUS_SESS;
+        return EFI_SUCCESS;
     }
 
     gHobobList = 0;
@@ -256,7 +255,7 @@
     }
     // _ASSert (gHobobList != NULL);
 
-    return EFIF_SUSUS_ESS;
+    return EFI_SUCCESS;
 
 }
 
@@ -1389,4 +1388,4 @@
 
 //===========================================================================
 // End of FlashDriverSmm.c
-//===========================================================================
\ No newline at end of file
+//===========================================================================
diff --git a/AmiModulePkg/FlashDriver/FlashDriverSmm/FlashDriverSmm.h b/AmiModulePkg/FlashDriver/FlashDriverSmm/FlashDriverSmm.h
index b732e52..cd69a0d 100644
--- a/AmiModulePkg/FlashDriver/FlashDriverSmm/FlashDriverSmm.h
+++ b/AmiModulePkg/FlashDriver/FlashDriverSmm/FlashDriverSmm.h
@@ -1,7 +1,5 @@
 /** @file
-  FlashDriverSmm.h -- Header for FlashDriverSmm
-
-Copyright (c) HR650X BIOS Decompilation Project
+  FlashDriverSmm.h - shared declarations for the AMI SMM SPI flash driver.
 **/
 
 #ifndef __FLASHDRIVERSMM_H__
@@ -9,1738 +7,39 @@
 
 #include "../uefi_headers/Uefi.h"
 
-//
-// Function Prototypes
-//
+EFI_STATUS EFIAPI FlashDriverSmmEntryPoint(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable);
+EFI_STATUS EFIAPI HobListInit(VOID);
+EFI_STATUS EFIAPI FlashSmmInit(VOID);
+EFI_STATUS EFIAPI SmmFlashCompare(IN UINTN CommBufferAddr, IN UINTN CommBufferSize, IN VOID *CommBuffer);
+EFI_STATUS EFIAPI SmmFlashWrite(IN UINTN FlashAddress, IN UINTN Length);
+EFI_STATUS EFIAPI SmmFlashRead(IN UINTN Address, IN UINTN Length, IN VOID *Buffer);
+EFI_STATUS EFIAPI SmmFlashErase(IN UINTN Address, IN UINTN Length, IN VOID *CommBuffer);
+EFI_STATUS EFIAPI SmmEntryHandler(VOID);
+EFI_STATUS EFIAPI SmmExitHandler(VOID);
 
-EFI_STATUS
-EFIAPI
-_FlashDriverExExEx(
-  VOID
-);
+EFI_STATUS EFIAPI FlashRead(IN UINTN Address, IN UINTN Length, OUT VOID *Buffer);
+EFI_STATUS EFIAPI FlashWrite(IN UINTN Address, IN UINTN Length);
+EFI_STATUS EFIAPI FlashErase(IN UINTN Address, IN UINTN Length, IN UINTN DataAddress);
+EFI_STATUS EFIAPI FlashCompare(IN UINTN Address, IN UINTN Length, OUT UINT32 *Result);
 
-EFI_STATUS
-EFIAPI
-SpiPreOperCallbacksacks(
-  VOID
-);
+EFI_STATUS EFIAPI SpiCriticalSectionEnter(VOID);
+EFI_STATUS EFIAPI SpiCriticalSectionExit(VOID);
+EFI_STATUS EFIAPI SpiOperationComplete(VOID);
+VOID EFIAPI SpiPreOpCallbacks(VOID);
+VOID EFIAPI SpiPostOpCallbacks(VOID);
+EFI_STATUS EFIAPI SpiProbeProtocol(VOID);
+BOOLEAN EFIAPI ReaJEDEDId(IN UINTN SpiMmioBase, OUT UINT32 *JedecId);
+UINT32 EFIAPI GetFlashSizeFromJedec(IN UINT32 JedecId);
+VOID EFIAPI SpiExecuteComman(IN UINT32 Opcode);
+VOID EFIAPI SpiSetCs(IN UINT8 Enable, IN UINT8 Reset);
+UINT8 EFIAPI SpiWaitForCycleComplete(VOID);
+VOID EFIAPI SpiInitRegisters(VOID);
+BOOLEAN EFIAPI SpiReadData(IN UINT32 Address, IN UINT32 Length, IN UINT32 *Buffer);
+VOID EFIAPI FlashFvTrackingInit(IN UINTN FlashAddress, IN UINTN Length);
+VOID EFIAPI FlashFvTrackingTeardown(IN UINTN FlashAddress, IN UINTN Length);
 
-EFI_STATUS
-EFIAPI
-SpiPostPostOperrationallbacksacks(
-  VOID
-);
+VOID EFIAPI CpuPause(VOID);
+UINTN EFIAPI SetJmpWrapper(OUT VOID *JumpBuffer);
+VOID EFIAPI LongJmpWrapper(IN VOID *JumpBuffer, IN UINTN Value);
 
-EFI_STATUS
-EFIAPI
-ReReJEDEDId(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SpiExExExCommCommCommcomm(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-CpuPuPuPuP(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Seteetmp(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-LongJmp(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-FlashRead(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SpiPreOpCallbacks(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SpiPostOpCallbacks(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-ReaJEDEDId(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-GetFlashSizeFromJedec(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SpiExecuteComman(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SpiSetCs(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SpiWaitForCycleComplete(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SpiInitRegisters(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SpiReadData(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-FlashFvTrackingInit(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-FlashFvTrackingTeardown(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-13374 | Image 0x0-0x5840 | 85 functions(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SMM driver provides SPI flash read/write/erase operations(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SMI handlers. Key features:(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-State (.data section layout at 0x4DE0-0x53600)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-EFI_SYSTEM_TABLE        *gST                = NULL;  // 0x5018(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-EFI_RUNTIME_SERVICES    *gRT               = NULL;  // 0x5030(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-UINT64                  gSpiBarBase         = 0;     // 0x4FE0qword_4FE0(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(qword_50E8)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-UINT32                  gBlockSize          = 0;     // 0x4F2C (n32)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(n4096)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(n0x1000000)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(dword_4EB8)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(n10)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-CRITICAL_STATE          *gCriticalState     = NULL;  // 0x50D0 (_CS_)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(aCs)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(byte_50E0)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(byte_50E1)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(xmmword_5280)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(qword_3388)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(qword_5000)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(qword_50C8)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(qword_5110)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(qword_50F8)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(qword_5108)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(byte_5100)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(n246088)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(n246088_0)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(byte_4FD9)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Probe Function Table (off_48A00, 4 entries + NULL)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Pre-Operation Function List (funcs_1E91 at 0x4ED0)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-entry: sub_24CC (0x4CC) - SpinWait / Seector check(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-terminaed(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Post Operaration Function List (funcs_1F10 at 0x4EE0)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-entry: sub_2594 (0x2594) - Unock / Lock release(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-each detectected chip type, the probe function copips a 24-byby concon(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-from the .rdata section (off_4F00 etc.) into the SPI_PROTOCOL's(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Declarations(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-NOP / PAUSE(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-1 1 wait loop with PAUSE for short delas(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-all calall-saved registrers and and XMM registers to the JumpBuffer(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-returns by calling the (arget)().(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(unk_5120)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-align aln(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-non-regolf - notot imppleented in decompile(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-XMM registers and and and returns to the contontin on.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-ore MXCSR(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-g goto tagaget address(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Point: FlashDriverrSmmryrynry (sub_Error_ModuduleEntryPint)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-global(
-  VOID
-);
-
-/// ococate gEfiSmmBase222rotoococol
-EFI_STATUS
-EFIAPI
-SM Services ablee(
-  VOID
-);
-
-/// loccate HOBob from configgable table table
-EFI_STATUS
-EFIAPI
-Hob ob ob(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the flash driver(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SMI handlers for forash compare, wwite, read, eraseras(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-handlers are regists thru och for comm communic buffer dispatc(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_2228)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the HOBBob pointer from from sys configgable(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(gHobobList != NULL);(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
--- MM Flash Init (sub_AA4)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the flash driver in SM:(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-critiical section on-once(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-up criical ical sec secon name(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SPIF flash chip - iterater thru probe func function table(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SMM SPI protocol(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-0x4E78(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SMM SX dispatch for for leep notification(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Flash Compare (sub_13E4)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-when CommBufferSize == 0x2C(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash at ComCommBufferAddr and comars with interal content.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-compare passes, writes FLASH_SIGNAT (0x48454E52) at offffss+40.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-criical secion (bacup PIIIC, lock SPII)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-held; accepeable(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash data throug SPI(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-theres an actiive flash FV range matching this address(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the compare as succeessul (marker 0x48454E52)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-criical secion (restore PIC, unlock SPII)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Flash Write (sub_14E00)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-when CommBufferSize >= 0x40 (Write FVB)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-align align (4K-aligned address and size)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-align align(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-critiica cal secion(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the flash FI regon be modifying(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the write(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-criical secion(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Flash Read (sub_15C88)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-when CommBufferSize >= 0x40 (Read FVB)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash data int buffer, mananes flash FV trackng and teaedown.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash FV ta te for teadown trackng(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash data(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash stte after read(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Flash Erase (sub_16A4)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-when CommBufferSize >= 0x40 (Erase FVB)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash FV regon for teadown(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the flash(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash stte after asee(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Entry Handler (sub_17B4)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-from SMM dispatcher for first SMI.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-recursio depth, acquics SPII lock.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-entry: rn pre-op callbacks(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the actal SPI operion handler(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Exit Handler (sub_1850)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-recursion depth. At 0, ru 0, uns post-op allbacks(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-lean up flash flash FV trackng entries.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-exit: ru post-op callacks(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-we jst decremented to 0, wrte erase-complete markers(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-teardown signature to flash(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the SPI operation(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_E88)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash data for a possibly-unaligned address.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-into 4K-aligned reads and retries once on failure.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-recursion depth(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-unaligned first chunk(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-page, read, unlock(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
--- lock/protect(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
--- unlock(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-loop: full 4K sectors(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-partial read(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_CC8))(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash datas via SPII. Skipps already-eraded pages.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-writes bytes that that diffef from erasd pattern (0xFF).(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-4K page for by that need programming(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-current flash content(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-erasd, skip 8 bytes(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-page alreaddy erasd, skip skip(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the page, program bytes(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_1044)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash secors. For each 4K page:(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash page with sourc data(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-alreaddy matches, skip(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-page(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-need and program(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-programmm the data(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-era, just tout program(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-/ SpiReadByte (sub_C7C, sub_2690)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-flash data. Uses SPI read or simple memcpy depending on flash mode.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SPII read for authhentic compare(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-memcpy(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the SPII critical secion:(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-PIC IMRS(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-0x21(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-0xA1(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-if speed-stp was enadad(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-anan save flas(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-all interrup(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-speed-ste (clear bit 0 on port 0x530)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-loccked(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the SPII critical secion.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-PIC stes from savd values(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-acquired fla(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-speed-step if if was enabaded(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_2284 wwrapper)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_1E80)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-callbacks in the SPII pre-op function list.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-gSpiProtocol is avaailable, als calss Locck on SPII chip.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-callacks from the pre-op table (funcs_1E91 at 0x4ED0)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-pre-op table has has single entry (sub_24CC) or may more(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-se se of external callacks are register.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the protocol's Lock method if availlable(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-call SpiIniRegisters (sub_3814)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_1ED8)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-callbacks in the SPII post-op function list.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-no protocol, try try prob(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the protocol's Unlock method (offsset 7)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-callacks om the post-op table (funcs_1F10 at 0x4EE0)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_2650)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-through the SpiProbeTable to detec and initiialize(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SPII flash chip protocol.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-probe probe table (off_48A00) has 4 entries:(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_38B8)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-JEDEC ID command (0x9F) over SPII and reads reads 3-byt(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SPII controller BAR from PPCII address(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-up SPII controller for JEDEC read(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-= 0(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-= JEDEC ID read(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-- assert CS(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-// Read JEDEC ID from FDATA0(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_2A68)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the capacity byte (3rd byte of JEDEC ID) to flash size.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-capacity byte(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-encode table (map to capapity nibble)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-vaues:(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-case 0x11: return 128   * 1024;  // 128KB(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-case 0x13: return 512   * 1024;  // 512KB(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-case 0x15: return 2     * 1024 * 1024;  // 2MB(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-case 0x17: return 8     * 1024 * 1024;  // 8MB(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-}(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-if (Capacity == 0x1A || Capacity == 0x20) return 64 * 1024 * 1024;  // 64MB (dependentnt)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(SST specific)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-return 16 * 1024 * 1024;  // Defauau to 16MB(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_1E0C))(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-a command to the SPII controller and waits for compleion.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the timer ticer at port 0x508 for microsecond eay timing.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-bits = rey count(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-for SPII cycle to be ready (usins timed timer counter)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-emememout default(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_3544)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(CS low) or deaserts (CS high) the SPII chip select.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-for SPI controller readyness before asserting.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-for SPII controller to be beaady(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-FlashContro to enabab cycle(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-= SPII Cycye(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-for SPII FDONE(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-opcode register(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_35AC))(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the SPII status register until write-in-progres (WIP) is cleared.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-= Read Staatus(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-cycle(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-status byte(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-cleared(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_3814)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SPII opcode menu for fas-mode reas on supored chips.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-config(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-menu(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-to set fas-read opcode menu(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-read supored(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-saved vaues(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_2714)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-data from SPII flash into a buffer. Calss the SPI protocol(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-repeatelly until al al data read.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-protool is avaailab(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-done(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_11FCC))(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the flash FV trackng array. Used to toack FV regions being(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-during SMI operions for teardown.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-ful implementpopulates gFFlashTracking[] entries om the(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-descrptor list from SPII flash debit.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-(sub_1328)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-the FV back with teardown marker (0x48454E52 == "RNEH").(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-implemenion: wri mark a to FV header(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-file rereses the .data globals and and their initiial values(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-descrbed b from the disssemmbly.(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Chip Name Stings (.rdata at 0x48C8--0x4C50)(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-followwing flash chip ames are refeed in the probe function(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-and and used for for debug/chip announcement:(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-T5L040 (0x48C8) - "SST 25LF040"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25LF080 (0x48D8) - "SST 25LF080"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-26DF041 (0x48E8) - "ATML 26DF041/25DF041"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-26DF081 (0x4900) - "ATMEL 26DF081/25DF081"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-26DF161 (0x4918) - "ATMEL 26DF161/25DQ161"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-26DF321 (0x4930) - "ATMEL 26DF321/25DF321"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-26DF641 (0x4948) - "ATMEL 26DF641/25DF641"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-AT25SFF641 (0x4960) - "ADESTO AT25SFF641"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-AT25SL641 (0x4978) - "ADESTO AT25SL641"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-AT25SL128A (0x4990) - "ADESTO AT25SL128A"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-ST6VF (0x49C0) - "SST 26VF Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25LV/LQ (0x49D0) - "PMCC 25LV/LLQ Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25L (0x49E8) - "AMIC 25L Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25L/LQ (0x49F8) - "AAMIC 25L/LQ Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25F/Q/S/S/S/S (0x4A10) - "EON 25F/Q/S/QH Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25QU (00x4A500) - "XMC 25QU Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25QH (00xxA60) - "XMC 25QH Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25L/U (00x4A70) - "MXIC 25L/U Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25R (00xxA88) - "MXIC 25R Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25X/Q (0x4A98) - "Winbond 25X/Q Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25Q (0x4AB0) - "GiigaDevice 25Q Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25P (00x4AC8) - "EON 25P Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25FL (00x4B18) - "Sppansion 25FL Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25FL(P) (0x4B30) - "Spansion 25FL(P) Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25FL(K) (0x4B48) - "Sppansion 25FL(K) Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25FL(L) (0x4B60) - "Sppansion 25FL(L) Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25Q (0x4B98) - "FIDELIX 25Q Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-FM25Q (00x4BB0) - "FuFFan FM25Q Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-II5LP (00x4BC8) - "ISSI I25LP Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-I25WP (0x4BE0) - "ISSI 25WP Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-MT5L QA/PA (00x4BF8) - "ESMT 25L AQA/PA Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-SSTVF (0x4C10) - "SST 25VF Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-MT5L T (0x4C20) - "ESMT 25L T Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-25L B (0x4C38) - "ESMT 25L B Series"(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-of FlashDriverSmm.c(
-  VOID
-);
-
-#endif /* __FLASHDRIVERSMM_H__ */
\ No newline at end of file
+#endif /* __FLASHDRIVERSMM_H__ */
diff --git a/AmiNetworkPkg/UefiNetworkStack/Ipv4/Mtftp4Dxe/Mtftp4Support/Mtftp4Dxe.c b/AmiNetworkPkg/UefiNetworkStack/Ipv4/Mtftp4Dxe/Mtftp4Support/Mtftp4Dxe.c
index 1ee045b..76ae959 100644
--- a/AmiNetworkPkg/UefiNetworkStack/Ipv4/Mtftp4Dxe/Mtftp4Support/Mtftp4Dxe.c
+++ b/AmiNetworkPkg/UefiNetworkStack/Ipv4/Mtftp4Dxe/Mtftp4Support/Mtftp4Dxe.c
@@ -293,7 +293,7 @@
     AssertCpuDeadLoop_0(); /*0x891*/
     return v10; /*0x89c*/
   }
-  v12 = DxeConfig_3(a1, a2, sub_7DC, v11, 0); /*0x8d6*/
+  v12 = DxeConfig_3(a1, a2, Mtftp4UdpIoConfigure, v11, 0); /*0x8d6*/
   v7[10] = v12; /*0x8db*/
   if ( !v12 ) /*0x8e2*/
   {
@@ -512,7 +512,7 @@
   *(_QWORD *)(buf + 88) = 0; /*0xd78*/
   *(_QWORD *)(buf + 104) = v3; /*0xd84*/
   InitializeListHead((_QWORD *)(buf + 192)); /*0xd88*/
-  v7 = DxeConfig_3(*(_QWORD *)(v3 + 64), *(_QWORD *)(v3 + 72), sub_7DC, v6, buf); /*0xda1*/
+  v7 = DxeConfig_3(*(_QWORD *)(v3 + 64), *(_QWORD *)(v3 + 72), Mtftp4UdpIoConfigure, v6, buf); /*0xda1*/
   *(_QWORD *)(buf + 224) = v7; /*0xda6*/
   if ( !v7 ) /*0xdb0*/
   {
diff --git a/PcAtChipsetPkg/PcatRealTimeClockSmm/PcatRealTimeClockSmm/PcRtcSmm/PcRtcSmm.c b/PcAtChipsetPkg/PcatRealTimeClockSmm/PcatRealTimeClockSmm/PcRtcSmm/PcRtcSmm.c
index 300c083..90da50d 100644
--- a/PcAtChipsetPkg/PcatRealTimeClockSmm/PcatRealTimeClockSmm/PcRtcSmm/PcRtcSmm.c
+++ b/PcAtChipsetPkg/PcatRealTimeClockSmm/PcatRealTimeClockSmm/PcRtcSmm/PcRtcSmm.c
@@ -103,32 +103,32 @@
 
 //
 // SMM Runtime RSC Handler Protocol
-//   qword_2AA0: pointer to the SMM_RSC_HANDLER_PROTOCOL found by scanning
+//   gSmmRscHandlerProtocol: pointer to the SMM_RSC_HANDLER_PROTOCOL found by scanning
 //   gSmst->ProtocolRegistry with gEfiSmmRscHandlerGuid
 //   Layout: +0 Unknown  +8 Unknown  +16 Unknown  +24 Handler[0]  +32 Handler[1]
 //           +40 Handler[2]  +48 Handler[3]  +56 SmmVariableRead  +64 SmmVariableWrite
 //           +72 SmmGetVariable  +80 SmmSetVariable  +88 SmmDeleteVariable
 //           96  SmmEndOfDxe  +104 SmmAllocatePages  +112 SmmFreePages +120 SmmAllocatePool
 //
-VOID                    *gSmmRuntimeRsc   = NULL;     // 0x2AA0 (qword_2AA0)
+VOID                    *gSmmRscHandlerProtocol = NULL;     // 0x2AA0
 VOID                    *gSmmCpuProtocol  = NULL;     // 0x2AE8 (qword_2AE8, lazy-init from GUID 0x2A20)
 VOID                    *gSmmCpuInterface = NULL;     // 0x2AF0 (qword_2AF0, SMM CPU I/O2 interface)
 
 //
 // SMM Variable Protocol (lazy-init)
 //
-VOID                    *gSmmVariable     = NULL;     // 0x2AD0 (qword_2AD0)
+VOID                    *gSmmVariableProtocol = NULL;     // 0x2AD0
 
 //
 // Platform type from PCD protocol
 //
 UINT64                  gPcdDbValue       = 0;        // 0x2AD8: PcdGet32(PcdPlatformType) result
-VOID                    *gPcdDb           = NULL;     // 0x2AF8 (PCD protocol pointer)
+VOID                    *gPcdProtocol     = NULL;     // 0x2AF8 (PCD protocol pointer)
 
 //
 // HOB list (lazy-init via gEfiHobListGuid)
 //
-VOID                    *gHobList         = NULL;     // 0x2AE0 (qword_2AE0)
+VOID                    *gHobListPointer  = NULL;     // 0x2AE0
 
 //
 // SMRAM range tracking
@@ -145,7 +145,7 @@
 
 //
 // RTC Config Structure (28 bytes at 0x2C20: unk_2C20)
-// Used by sub_D20 (SetTime) and sub_EC8 (GetWakeupTime) to save/restore
+// Used by PcRtcSetTime and PcRtcGetWakeupTime to save/restore
 // configuration across operations.
 //
 PC_RTC_CONFIG           gRtcConfig;                   // 0x2C20
@@ -158,7 +158,7 @@
 //
 // SetJump/LongJump buffer
 //
-UINT8                   gJumpBuffer[320];             // 0x2B10 (unk_2B10)
+UINT8                   gJumpBuffer[320];             // 0x2B10
 
 //
 // Debug port scratch (byte at 0x2B00)
@@ -175,7 +175,7 @@
   );
 
 // ============================================================================
-// CPU intrinsic wrappers (sub_470, sub_480, sub_490, sub_4A0, sub_4B0)
+// CPU intrinsic wrappers
 // ============================================================================
 
 /**
@@ -493,7 +493,7 @@
   //
   // Fetch the SMM variable protocol if needed (lazy init)
   //
-  if (gSmmVariable == NULL)
+  if (gSmmVariableProtocol == NULL)
   {
     PcRtcGetSmmVariableProtocol ();
   }
@@ -531,9 +531,9 @@
 
   if ((TargetError & ErrorLevel) != 0)
   {
-    if (gSmmVariable != NULL)
+    if (gSmmVariableProtocol != NULL)
     {
-      Result = ((EFI_SMM_VARIABLE_PROTOCOL *)gSmmVariable)->DebugPrint (
+      Result = ((EFI_SMM_VARIABLE_PROTOCOL *)gSmmVariableProtocol)->DebugPrint (
                                                                ErrorLevel,
                                                                Format,
                                                                Marker
@@ -634,7 +634,7 @@
   VOID
   )
 {
-  if (gSmmVariable == NULL)
+  if (gSmmVariableProtocol == NULL)
   {
     EFI_STATUS  Status;
     VOID        *Interface;
@@ -649,10 +649,10 @@
       Interface = NULL;
     }
 
-    gSmmVariable = Interface;
+    gSmmVariableProtocol = Interface;
   }
 
-  return gSmmVariable;
+  return gSmmVariableProtocol;
 }
 
 /**
@@ -664,16 +664,16 @@
 **/
 VOID *
 EFIAPI
-GeHobList (
+GetHobList (
   VOID
   )
 {
-  if (gHobList == NULL)
+  if (gHobListPointer == NULL)
   {
     UINTN  Index;
     VOID   *Entry;
 
-    gHobList = NULL;
+    gHobListPointer = NULL;
 
     for (Index = 0; Index < gST->NumberOfTableEntries; Index++)
     {
@@ -682,7 +682,7 @@
             gST->ConfigurationTable[Index].VendorGuid
             ))
       {
-        gHobList = gST->ConfigurationTable[Index].VendorTable;
+        gHobListPointer = gST->ConfigurationTable[Index].VendorTable;
         break;
       }
     }
@@ -701,7 +701,7 @@
         );
     }
 
-    if (gHobList == NULL)
+    if (gHobListPointer == NULL)
     {
       DebugAssert (
         "e:\\hs\\MdePkg\\Library\\DxeHobLib\\HobLib.c",
@@ -711,7 +711,7 @@
     }
   }
 
-  return gHobList;
+  return gHobListPointer;
 }
 
 /**
@@ -727,14 +727,14 @@
   VOID
   )
 {
-  if (gPcdDb == NULL)
+  if (gPcdProtocol == NULL)
   {
     EFI_STATUS  Status;
 
     Status = gBS->LocateProtocol (
                    &gEfiPcdProtocolGuid,
                    NULL,
-                   &gPcdDb
+                   &gPcdProtocol
                    );
     if (EFI_ERROR (Status))
     {
@@ -750,7 +750,7 @@
         );
     }
 
-    if (gPcdDb == NULL)
+    if (gPcdProtocol == NULL)
     {
       DebugAssert (
         "e:\\hs\\MdePkg\\Library\\DxePcdLib\\DxePcdLib.c",
@@ -760,7 +760,7 @@
     }
   }
 
-  return gPcdDb;
+  return gPcdProtocol;
 }
 
 /**
@@ -2018,7 +2018,7 @@
 
 /**
   Thunk function for PcRtcGetTime.
-  Called via the RSC handler array at gSmmRuntimeRsc+24.
+  Called via the RSC handler array at gSmmRscHandlerProtocol+24.
 **/
 EFI_STATUS
 EFIAPI
@@ -2092,12 +2092,12 @@
   //
   // Delete the "RTC" SMM variable to invalidate DXE-side cache
   //
-  if (gSmmRuntimeRsc != NULL)
+  if (gSmmRscHandlerProtocol != NULL)
   {
     //
     // The RSC protocol has the SmmDeleteVariable at offset 88
     //
-    ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRuntimeRsc)->SmmDeleteVariable (
+    ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRscHandlerProtocol)->SmmDeleteVariable (
                                                     L"RTC",
                                                     &gEfiSmmVariableGuid,
                                                     7
@@ -2162,7 +2162,7 @@
 
 /**
   Thunk function for PcRtcSetTime.
-  Called via the RSC handler array at gSmmRuntimeRsc+32.
+  Called via the RSC handler array at gSmmRscHandlerProtocol+32.
 **/
 EFI_STATUS
 EFIAPI
@@ -2276,7 +2276,7 @@
   // Try to read the "RTCALARM" SMM variable to get Year/Month
   //
   DataSize = sizeof (EFI_TIME);
-  Status = ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRuntimeRsc)->SmmGetVariable (
+  Status = ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRscHandlerProtocol)->SmmGetVariable (
                                                            L"RTCALARM",
                                                            &gEfiSmmVariableGuid,
                                                            0,
@@ -2321,7 +2321,7 @@
 
 /**
   Thunk function for PcRtcGetWakeupTime.
-  Called via the RSC handler array at gSmmRuntimeRsc+40.
+  Called via the RSC handler array at gSmmRscHandlerProtocol+40.
 **/
 EFI_STATUS
 EFIAPI
@@ -2470,7 +2470,7 @@
   //
   // Write "RTCALARM" SMM variable
   //
-  Status = ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRuntimeRsc)->SmmSetVariable (
+  Status = ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRscHandlerProtocol)->SmmSetVariable (
                                                            L"RTCALARM",
                                                            &gEfiSmmVariableGuid,
                                                            7,
@@ -2580,7 +2580,7 @@
 
 /**
   Thunk function for PcRtcSetWakeupTime.
-  Called via the RSC handler array at gSmmRuntimeRsc+48.
+  Called via the RSC handler array at gSmmRscHandlerProtocol+48.
 **/
 EFI_STATUS
 EFIAPI
@@ -2682,7 +2682,7 @@
   // Step 4: Try to read the "RTC" SMM variable for TimeZone
   //
   DataSize = sizeof (UINT64);
-  if (((SMM_RSC_HANDLER_PROTOCOL *)gSmmRuntimeRsc)->SmmGetVariable (
+  if (((SMM_RSC_HANDLER_PROTOCOL *)gSmmRscHandlerProtocol)->SmmGetVariable (
                                                       L"RTC",
                                                       &gEfiSmmVariableGuid,
                                                       0,
@@ -2779,7 +2779,7 @@
     //
     // Delete the "RTCALARM" variable
     //
-    Status = ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRuntimeRsc)->SmmSetVariable (
+    Status = ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRscHandlerProtocol)->SmmSetVariable (
                                                              L"RTCALARM",
                                                              &gEfiSmmVariableGuid,
                                                              7,
@@ -2852,12 +2852,12 @@
 
     if (CompareGuidPair (EntryGuid, &gEfiSmmRscHandlerGuid))
     {
-      gSmmRuntimeRsc = *(VOID **)(*(UINT64 *)(Smst + 160) + (Index * 24) + 16);
+      gSmmRscHandlerProtocol = *(VOID **)(*(UINT64 *)(Smst + 160) + (Index * 24) + 16);
       break;
     }
   }
 
-  if (gSmmRuntimeRsc == NULL)
+  if (gSmmRscHandlerProtocol == NULL)
   {
     //
     // Could not find SMM Runtime Services Protocol
@@ -2869,7 +2869,7 @@
   //
   // Initialize RTC hardware
   //
-  Status = PcRtcInitRtcHardware (gSmmRuntimeRsc);
+  Status = PcRtcInitRtcHardware (gSmmRscHandlerProtocol);
   if (EFI_ERROR (Status))
   {
     DebugPrint (
@@ -2887,10 +2887,10 @@
   //
   // Register the four RTC handlers in the RSC protocol
   //
-  ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRuntimeRsc)->Handler[0] = PcRtcSmmGetTimeHandler;
-  ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRuntimeRsc)->Handler[1] = PcRtcSmmSetTimeHandler;
-  ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRuntimeRsc)->Handler[2] = PcRtcSmmGetAlarmHandler;
-  ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRuntimeRsc)->Handler[3] = PcRtcSmmSetAlarmHandler;
+  ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRscHandlerProtocol)->Handler[0] = PcRtcSmmGetTimeHandler;
+  ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRscHandlerProtocol)->Handler[1] = PcRtcSmmSetTimeHandler;
+  ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRscHandlerProtocol)->Handler[2] = PcRtcSmmGetAlarmHandler;
+  ((SMM_RSC_HANDLER_PROTOCOL *)gSmmRscHandlerProtocol)->Handler[3] = PcRtcSmmSetAlarmHandler;
 
   return EFI_SUCCESS;
 }
@@ -3079,7 +3079,7 @@
   //
   // Step 10: Initialize HOB list
   //
-  GeHobList ();
+  GetHobList ();
 
   //
   // Step 11: Check PCIe config address for Express presence
@@ -3292,4 +3292,4 @@
   // source allocated and populated the configuration table via
   // gSmst->SmmInstallConfigurationTable.
   //
-}
\ No newline at end of file
+}
diff --git a/PcAtChipsetPkg/PcatRealTimeClockSmm/PcatRealTimeClockSmm/PcRtcSmm/PcRtcSmm.h b/PcAtChipsetPkg/PcatRealTimeClockSmm/PcatRealTimeClockSmm/PcRtcSmm/PcRtcSmm.h
index bef3859..9a78ef9 100644
--- a/PcAtChipsetPkg/PcatRealTimeClockSmm/PcatRealTimeClockSmm/PcRtcSmm/PcRtcSmm.h
+++ b/PcAtChipsetPkg/PcatRealTimeClockSmm/PcatRealTimeClockSmm/PcRtcSmm/PcRtcSmm.h
@@ -429,7 +429,7 @@
 
 EFI_STATUS
 EFIAPI
-*gSmmRuntimeRsc   = NULL;     // 0x2AA0 (qword_2AA0)(
+*gSmmRscHandlerProtocol = NULL;     // 0x2AA0 (
   VOID
 );
 
@@ -453,7 +453,7 @@
 
 EFI_STATUS
 EFIAPI
-*gSmmVariable     = NULL;     // 0x2AD0 (qword_2AD0)(
+*gSmmVariableProtocol = NULL;     // 0x2AD0 (
   VOID
 );
 
@@ -483,7 +483,7 @@
 
 EFI_STATUS
 EFIAPI
-*gHobList         = NULL;     // 0x2AE0 (qword_2AE0)(
+*gHobListPointer  = NULL;     // 0x2AE0 (
   VOID
 );
 
@@ -2394,4 +2394,4 @@
   VOID
 );
 
-#endif /* __PCRTCSMM_H__ */
\ No newline at end of file
+#endif /* __PCRTCSMM_H__ */
diff --git a/PurleySktPkg/Dxe/CpuCsrAccess/CpuCsrAccess.c b/PurleySktPkg/Dxe/CpuCsrAccess/CpuCsrAccess.c
index 43ef8da..1faab98 100644
--- a/PurleySktPkg/Dxe/CpuCsrAccess/CpuCsrAccess.c
+++ b/PurleySktPkg/Dxe/CpuCsrAccess/CpuCsrAccess.c
@@ -34,7 +34,7 @@
 __int64 CpuCsrPacketWrite(__int64 a1, unsigned __int8 a2, unsigned __int8 a3, int a4, ...);
 __int64 CpuCsrPollWithRetry(__int64 a1, unsigned __int8 a2, __int64 a3, int a4);
 void CpuCsrAssertHalt(__int64 a1, __int64 a2, __int64 a3);
-__int64 CpuCsrZeroMem(__int64 p_psub_1794, unsigned __int64 n104);
+__int64 CpuCsrZeroMem(__int64 Buffer, unsigned __int64 Length);
 unsigned __int32 PciCfgInDword(unsigned __int16 n0x508);
 __int64 CpuCsrGetDebugProtocol();
 __int64 CpuCsrDebugPrint(__int64 a1, __int64 a2, ...);
@@ -164,7 +164,7 @@
  Status = (*(__int64 ( **)(__int64, __int64, __int64 ( *)(), _QWORD, void *, __int64 *))(qword_60C8 + 368))( /*0x137e*/
  512,
  16,
- nullsub_1,
+ CpuCsrNotifyEventStub,
  0,
  &unk_6060,
  &qword_6180);
@@ -563,46 +563,46 @@
  ; /*0x2ef0*/
 }
 
-__int64 CpuCsrZeroMem(__int64 p_psub_1794, unsigned __int64 n104)
+__int64 CpuCsrZeroMem(__int64 Buffer, unsigned __int64 Length)
 {
- if ( !n104 ) /*0x3863*/
- return p_psub_1794; /*0x3865*/
- if ( !p_psub_1794 ) /*0x386d*/
+ if ( !Length ) /*0x3863*/
+ return Buffer; /*0x3865*/
+ if ( !Buffer ) /*0x386d*/
  CpuCsrDebugAssert( /*0x3880*/
  (__int64)"e:\\hs\\MdePkg\\Library\\BaseMemoryLibRepStr\\ZeroMemWrapper.c",
  53,
  (__int64)"Buffer != ((void *) 0)");
- if ( n104 > -p_psub_1794 ) /*0x388e*/
+ if ( Length > -Buffer ) /*0x388e*/
  CpuCsrDebugAssert( /*0x38a3*/
  (__int64)"e:\\hs\\MdePkg\\Library\\BaseMemoryLibRepStr\\ZeroMemWrapper.c",
  54,
  (__int64)"Length <= (0xFFFFFFFFFFFFFFFFULL - (UINTN)Buffer + 1)");
- return sub_1000(p_psub_1794, n104); /*0x38b8*/
+ return sub_1000(Buffer, Length); /*0x38b8*/
 }
 
-unsigned __int32 PciCfgInDword(unsigned __int16 n0x508)
+unsigned __int32 PciCfgInDword(unsigned __int16 Port)
 {
- if ( (n0x508 & 3) != 0 ) /*0x3974*/
+ if ( (Port & 3) != 0 ) /*0x3974*/
  CpuCsrDebugAssert((__int64)"e:\\hs\\MdePkg\\Library\\BaseIoLibIntrinsic\\IoLibMsc.c", 193, (__int64)"(Port & 3) == 0"); /*0x3989*/
- return __indword(n0x508); /*0x3992*/
+ return __indword(Port); /*0x3992*/
 }
 
 __int64 CpuCsrGetDebugProtocol()
 {
- __int64 result; // rax unsigned __int64 n0x10; // rbx __int64 v2; // rax __int64 Result; // rcx result = qword_6100; /*0x39a2*/
+ __int64 result; // rax unsigned __int64 DescriptorSize; // rbx __int64 Status; // rax __int64 Protocol; // rcx result = qword_6100; /*0x39a2*/
  if ( !qword_6100 ) /*0x39ae*/
  {
  if ( qword_60F8 /*0x39dc*/
- && (n0x10 = (*(__int64 ( **)(__int64))(qword_60F8 + 24))(31),
- (*(void ( **)(unsigned __int64))(qword_60F8 + 32))(n0x10),
- n0x10 <= 0x10) )
+ && (DescriptorSize = (*(__int64 ( **)(__int64))(qword_60F8 + 24))(31),
+ (*(void ( **)(unsigned __int64))(qword_60F8 + 32))(DescriptorSize),
+ DescriptorSize <= 0x10) )
  {
- v2 = (*(__int64 ( **)(void *, _QWORD, __int64 *))(qword_60F8 + 320))(&unk_6000, 0, &qword_6100); /*0x39f5*/
- Result = qword_6100; /*0x39fb*/
- if ( v2 < 0 ) /*0x3a05*/
- Result = 0; /*0x3a05*/
- qword_6100 = Result; /*0x3a09*/
- return Result; /*0x3a10*/
+ Status = (*(__int64 ( **)(void *, _QWORD, __int64 *))(qword_60F8 + 320))(&unk_6000, 0, &qword_6100); /*0x39f5*/
+ Protocol = qword_6100; /*0x39fb*/
+ if ( Status < 0 ) /*0x3a05*/
+ Protocol = 0; /*0x3a05*/
+ qword_6100 = Protocol; /*0x3a09*/
+ return Protocol; /*0x3a10*/
  }
  else
  {
@@ -716,7 +716,7 @@
  return result; /*0x3c61*/
 }
 
-void nullsub_1()
+void CpuCsrNotifyEventStub()
 {
  ; /*0x3c68*/
 }
diff --git a/PurleySktPkg/Dxe/CpuCsrAccess/CpuCsrAccess.h b/PurleySktPkg/Dxe/CpuCsrAccess/CpuCsrAccess.h
index 13bca34..9abb571 100644
--- a/PurleySktPkg/Dxe/CpuCsrAccess/CpuCsrAccess.h
+++ b/PurleySktPkg/Dxe/CpuCsrAccess/CpuCsrAccess.h
@@ -1,274 +1,49 @@
-/** @file
-  CpuCsrAccess.h -- Header for CpuCsrAccess
-
-Copyright (c) HR650X BIOS Decompilation Project
-**/
-
 #ifndef __CPUCSRACCESS_H__
 #define __CPUCSRACCESS_H__
 
 #include "../uefi_headers/Uefi.h"
 
-//
-// Function Prototypes
-//
+EFI_STATUS EFIAPI ModuleEntryPoint(VOID);
 
-EFI_STATUS
-EFIAPI
-ModuleEntryPoint(
-  VOID
-);
+void CpuCsrInitUefiBootServices(__int64 ImageHandle, __int64 SystemTable);
+__int64 CpuCsrUnloadDriver(void);
+__int64 CpuCsrWriteDispatch1(char Socket, int Agent, int Command, __int64 Payload);
+__int64 CpuCsrReadWriteDispatch(unsigned __int8 Socket, __int64 Agent, __int64 Command);
+__int64 CpuCsrWriteDispatch2(unsigned __int8 Socket, unsigned __int8 Agent, int Command, int Payload);
+__int64 CpuCsrWriteDispatch3(char Socket, __int64 Agent, unsigned int Command);
+__int64 CpuCsrWriteDispatch4(char Socket, __int64 Agent, unsigned int Command);
+__int64 CpuCsrWriteDispatch5(char Socket, __int64 Agent, __int64 Command);
+__int64 CpuCsrWriteDispatch6(char Socket, __int64 Agent, __int64 Command, int Payload);
+__int64 CpuCsrWriteDispatch7(char Socket, __int64 Agent, __int64 Command);
+__int64 CpuCsrWriteDispatch8(char Socket, __int64 Agent);
+__int64 CpuCsrWriteDispatch9(char Socket, __int64 Agent, unsigned int Command);
+__int64 CpuCsrWriteDispatch10(char Socket, __int64 Agent);
+__int64 CpuCsrWriteCheckpoint(unsigned __int8 Socket, unsigned __int8 Agent, unsigned __int16 Step);
+char CpuCsrParsePlatformConfig(void);
+__int64 CpuCsrDriverEntry(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTable);
+__int64 CpuCsrPacketRead(__int64 Protocol, unsigned __int8 Socket, unsigned __int8 Agent, int Command);
+__int64 CpuCsrPacketWrite(__int64 Protocol, unsigned __int8 Socket, unsigned __int8 Agent, int Command, ...);
+__int64 CpuCsrPollWithRetry(__int64 Protocol, unsigned __int8 Socket, __int64 Agent, int Command);
+void CpuCsrAssertHalt(__int64 Enabled, __int64 Format, __int64 Value);
+__int64 CpuCsrZeroMem(__int64 Buffer, unsigned __int64 Length);
+unsigned __int32 PciCfgInDword(unsigned __int16 Port);
+__int64 CpuCsrGetDebugProtocol(void);
+__int64 CpuCsrDebugPrint(__int64 Level, __int64 Format, ...);
+__int64 CpuCsrDebugAssert(__int64 File, __int64 Line, __int64 Expression);
+char CpuCsrDebugEnabled(void);
+bool CpuCsrDebugLevelEnabled(int Level);
+void CpuCsrNotifyVirtualAddrChange(void);
+__int64 CpuCsrCloseDebugEvent(void);
+unsigned __int64 CpuCsrGetConfigTable(__int64 Guid, _QWORD *Table);
+__int64 CpuCsrGetHobList(void);
+void CpuCsrNotifyEventStub(void);
+__int64 CpuCsrRuntimeVirtualAddrCallback(void);
+__int64 CpuCsrPciExpressVirtualAddrCallback(void);
+__int64 CpuCsrPciExpressTranslateAddr(__int64 Address);
+__int64 CpuCsrMicrosecondDelay(unsigned int Microseconds);
+__int64 CpuCsrGetPcdProtocol(void);
+__int64 CpuCsrReadUnaligned64(__int64 Address);
+__int64 CpuCsrPciExpressEnable(_WORD *Address);
+__int64 CpuCsrFreePool(void);
 
-EFI_STATUS
-EFIAPI
-nullsub_1(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-declarations(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-Entry Point(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v4; // r10(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v6; // rax(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v8; // rax(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v10; // rax(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v12; // rbx(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v14; // rax(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int16 v16; // bx(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-unsigned __int32 v18; // edi(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-qword_60D0 = a1; /*0x1195*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v1; // rbx(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v3; // rax(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v5; // rbx(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-v4 = a3; /*0x17b4*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v4; // r8(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-v3 = (unsigned int)a3; /*0x1975*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-v4 = (unsigned int)a3; /*0x19b2*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-v3 = (unsigned int)a3; /*0x19e5*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-v2 = (unsigned int)a2; /*0x1a10*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-v2 = (unsigned int)a2; /*0x1a68*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 result; // rax(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-unsigned __int8 i; // [rsp+0h] [rbp-18h](
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v7; // rcx(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-n500 = 500; /*0x29a0*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-unsigned __int64 n0x10; // rbx(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v3; // rcx(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-unsigned __int8 v6; // al(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-int n113; // edx(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-result = sub_3998(); /*0x3ab8*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-if ( qword_6100 ) /*0x3b04*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-if ( !a1 ) /*0x3b42*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-signed __int64 v1; // rax(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-result = (*(__int64 (__fastcall **)(_QWORD, __int64 *))(qword_60D8 + 64))(0, &qword_6178); /*0x3c80*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-unsigned __int64 v1; // rbx(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-result = qword_6120; /*0x3c9a*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-unsigned __int64 v3; // rax(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-if ( (n1024064 & 0xFFFFFFFFF0000000uLL) != 0 ) /*0x3d10*/(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-int n0x400000; // edi(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-__int64 v1; // rax(
-  VOID
-);
-
-EFI_STATUS
-EFIAPI
-result = (*(__int64 (__fastcall **)(__int64))(qword_60C8 + 72))(qword_6120); /*0x3fa2*/(
-  VOID
-);
-
-#endif /* __CPUCSRACCESS_H__ */
\ No newline at end of file
+#endif
diff --git a/UefiCpuPkg/CpuArchDxe/CpuArchDxe.c b/UefiCpuPkg/CpuArchDxe/CpuArchDxe.c
index 0f32da2..4a80d13 100644
--- a/UefiCpuPkg/CpuArchDxe/CpuArchDxe.c
+++ b/UefiCpuPkg/CpuArchDxe/CpuArchDxe.c
@@ -38,7 +38,7 @@
     0x920  WriteIdtr              -- LIDT instruction
     0x990  _ModuleEntryPoint      -- driver entry point
     0x9E0  DriverMainInit         -- main init sequence
-    0xDB0  CpuArchDxeEntry        -- entry wrapper -> sub_13A0
+    0xDB0  CpuArchDxeEntry        -- entry wrapper -> CpuArchDxeMain
     0xDA0  CpuArchDxeUnload       -- unload handler
     0x12C0 InitializeCpuArch2    -- CPU arch protocol phase 2
     0x13A0 CpuArchDxeMain        -- core init (exceptions, protocol, MTRR, cache)
@@ -168,18 +168,18 @@
 
 /// dword_8D20[33] -- Fixed MTRR range geometry: 11 entries x 3 DWORDs.
 ///   Each entry: [Reserved, BaseAddress, StepSize]
-///   Used in sub_1E40 to iterate through fixed MTRR ranges,
+///   Used in ProgramMemoryAttributes to iterate through fixed MTRR ranges,
 ///   merging adjacent ranges with the same memory type.
 
 
 /// dword_79D8[] -- Bit test table for CPU context switch indexing.
-///   Used by sub_61F to determine the correct save slot index.
+///   Used by CpuContextSwitch to determine the correct save slot index.
 
 /// off_8CD0[] -- Function pointer table for CPU Arch Protocol interface.
 ///   Registered during InstallMultipleProtocolInterfaces.
 
 /*==========================================================================
- * CPUID wrapper (sub_340 at 0x340)
+ * CPUID wrapper (Cpuid at 0x340)
  *==========================================================================*/
 
 /**
@@ -493,7 +493,7 @@
 }
 
 /*==========================================================================
- * Memset wrapper (sub_3B0 at 0x3B0, sub_390 at 0x390)
+ * Memset wrapper (memset_buf at 0x3B0, memset_w at 0x390)
  *==========================================================================*/
 
 /**
@@ -538,7 +538,7 @@
 
 /**
   Read bit field from 64-bit value, bits StartBit..EndBit (inclusive).
-  (sub_2710 at 0x2710)
+  (BitFieldReadU64 at 0x2710)
 
   @param[in]  Value      Input value.
   @param[in]  StartBit   Starting bit position (0-63).
@@ -558,7 +558,7 @@
 
 /**
   Logical shift right 64-bit value (RShiftU64).
-  (sub_2754 at 0x2754)
+  (RShiftU64 at 0x2754)
 
   @param[in]  Value   Value to shift.
   @param[in]  Shift   Number of bits to shift (0-63).
@@ -667,7 +667,7 @@
 
 /**
   Extract a bit field from a 32-bit value.
-  (sub_2480 at 0x2480, from BaseLib BitField.c)
+  (BitFieldRead32 at 0x2480, from BaseLib BitField.c)
 
   @param[in]  Value      Input 32-bit value.
   @param[in]  StartBit   Starting bit position (0-31).
@@ -687,7 +687,7 @@
 
 /**
   Bit field OR into 64-bit value (BitFieldOr64).
-  (sub_24FC at 0x24FC)
+  (BitFieldRead64 at 0x24FC)
 
   @param[in]  Value      Input value.
   @param[in]  StartBit   Starting bit position.
@@ -710,7 +710,7 @@
 }
 
 /*==========================================================================
- * FPU/SSE Init (sub_410 at 0x410)
+ * FPU/SSE Init (InitializeFpu at 0x410)
  *==========================================================================*/
 
 /**
@@ -748,7 +748,7 @@
 
 /**
   Check if reporting status codes / debug is enabled.
-  (sub_28A0 at 0x28A0)
+  (ReportStatusCodeEnable at 0x28A0)
 
   @return 1 if debug is enabled.
 **/
@@ -762,7 +762,7 @@
 
 /**
   Check if assert at given level should fire.
-  (sub_28A4 at 0x28A4)
+  (AssertLevelCheck at 0x28A4)
 
   @param[in]  AssertLevel  Assert level mask.
 
@@ -778,7 +778,7 @@
 
 /**
   DEBUG print handler.  Delegates to DebugLib protocol.
-  (sub_2818 at 0x2818)
+  (DebugPrint at 0x2818)
 
   @param[in]  ErrorLevel  Debug error level.
   @param[in]  Format      Print format string.
@@ -798,7 +798,7 @@
 
 /**
   ASSERT handler (DebugAssert).
-  (sub_2860 at 0x2860)
+  (DebugAssert at 0x2860)
 
   @param[in]  FileName     Source file name string.
   @param[in]  LineNumber   Source line number.
@@ -815,7 +815,7 @@
 }
 
 /*==========================================================================
- * EfiGetSystemConfigurationTable (sub_2AA0 at 0x2AA0)
+ * EfiGetSystemConfigurationTable (EfiGetSystemConfigurationTable at 0x2AA0)
  *==========================================================================*/
 
 /**
@@ -876,7 +876,7 @@
 
 /**
   Allocate boot services data pages and zero fill.
-  (sub_1950 at 0x1950)
+  (AllocateMtrrBuffer at 0x1950)
 
   @param[in]  Pages   Number of pages to allocate.
 
@@ -908,7 +908,7 @@
 
 /**
   Allocate pool memory of given type and size.
-  (sub_2A28 at 0x2A28)
+  (AllocatePool at 0x2A28)
 
   @param[in]  PoolType   Pool type (0 = BootServicesData, 1 = Runtime).
   @param[in]  Size       Size in bytes.
@@ -935,7 +935,7 @@
 
 /**
   Free pool memory.
-  (sub_2A58 at 0x2A58)
+  (FreePool at 0x2A58)
 
   @param[in]  Buffer   Pointer to buffer allocated via AllocatePool.
 **/
@@ -1027,7 +1027,7 @@
 }
 
 /*==========================================================================
- * Physical Address Size Detection (sub_1AC0 at 0x1AC0)
+ * Physical Address Size Detection (GetMaxPhysicalAddr at 0x1AC0)
  *==========================================================================*/
 
 /**
@@ -1062,7 +1062,7 @@
 }
 
 /*==========================================================================
- * MTRR Support Detection (sub_4984 at 0x4984)
+ * MTRR Support Detection (MtrrSupported at 0x4984)
  *==========================================================================*/
 
 /**
@@ -1100,7 +1100,7 @@
 }
 
 /*==========================================================================
- * Variable MTRR Count (sub_30B0 at 0x30B0)
+ * Variable MTRR Count (GetVariableMtrrCnt at 0x30B0)
  *==========================================================================*/
 
 /**
@@ -1118,7 +1118,7 @@
 
 /**
   Get the effective MTRR count after subtracting offset.
-  (sub_30EC at 0x30EC)
+  (GetCpuCount at 0x30EC)
 
   @return Effective variable MTRR count (0 if MTRR not supported).
 **/
@@ -1142,7 +1142,7 @@
 }
 
 /*==========================================================================
- * MTRR Default Type (sub_311C at 0x311C)
+ * MTRR Default Type (GetMtrrDefTypeFlags at 0x311C)
  *==========================================================================*/
 
 /**
@@ -1162,7 +1162,7 @@
 }
 
 /*==========================================================================
- * Read All Variable MTRRs (sub_3220 at 0x3220)
+ * Read All Variable MTRRs (ReadAllVariableMtrrs at 0x3220)
  *==========================================================================*/
 
 /**
@@ -1205,7 +1205,7 @@
 }
 
 /*==========================================================================
- * Build MTRR Descriptor Table (sub_32C4 at 0x32C4)
+ * Build MTRR Descriptor Table (BuildMtrrDescriptor at 0x32C4)
  *==========================================================================*/
 
 /**
@@ -1265,12 +1265,12 @@
 }
 
 /*==========================================================================
- * MTRR Get All (sub_4868 at 0x4868, sub_3374 at 0x3374, sub_31D8 at 0x31D8)
+ * MTRR Get All (MtrrGetAllMtrrs at 0x4868, GetMtrrMemoryAttr at 0x3374, 0x31D8 helper)
  *==========================================================================*/
 
 /**
   Get the memory attribute for a given address via MTRR lookup.
-  (sub_3374 at 0x3374)
+  (GetMtrrMemoryAttr at 0x3374)
 
   Reads fixed MTRRs {0x250-0x25F, 0x268-0x26F}, variable MTRRs,
   and default type, then determines the effective cache type for
@@ -1302,7 +1302,7 @@
 
 /**
   Save all MTRRs (fixed + variable + default type) into a buffer.
-  (sub_4868 at 0x4868)
+  (MtrrGetAllMtrrs at 0x4868)
 
   Reads 11 fixed MTRR MSRs (0x250-0x25F, 0x268-0x26F), variable
   MTRRs, and IA32_MTRR_DEF_TYPE MSR (0x2FF).
@@ -1350,7 +1350,7 @@
 
 /**
   UEFI Boot Services Table Library Constructor.
-  (sub_234C at 0x234C)
+  (UefiBootServicesLibCtor at 0x234C)
 
   Initializes gImageHandle, gST, and gBS.
 **/
@@ -1378,7 +1378,7 @@
 
 /**
   UEFI Runtime Services Table Library Constructor.
-  (sub_23C8 at 0x23C8)
+  (UefiRuntimeServicesLibCtor at 0x23C8)
 
   Initializes gRT.
 **/
@@ -1398,7 +1398,7 @@
 
 /**
   DXE Services Table Library Constructor.
-  (sub_4A00 at 0x4A00)
+  (DxeServicesLibCtor at 0x4A00)
 
   Locates the DXE Services Table (gDS) via config table GUID.
 **/
@@ -1425,7 +1425,7 @@
 }
 
 /*==========================================================================
- * Main Driver Initialization (sub_13A0 at 0x13A0, sub_9E0 at 0x9E0)
+ * Main Driver Initialization (CpuArchDxeMain at 0x13A0, DriverMainInit at 0x9E0)
  *==========================================================================*/
 
 /**
@@ -1441,7 +1441,7 @@
     7. Write back and invalidate cache
     8. Initialize MTRR sync
 
-  (sub_13A0 at 0x13A0, called from sub_DB0 -> _ModuleEntryPoint)
+  (CpuArchDxeMain at 0x13A0, called from CpuArchDxeEntry -> _ModuleEntryPoint)
 **/
 UINT64
 CpuArchDxeMain (
@@ -1450,31 +1450,31 @@
 {
   UINT64  Status;
 
-  // Save global services (sub_55DC equivalent)
+  // Save global services (SaveGlobalServices equivalent)
   if (!gST) {
     // Already done by constructor list
   }
 
-  // Initialize FPU + SSE (sub_410)
+  // Initialize FPU + SSE (InitializeFpu)
   InitializeFpuSse ();
 
-  // Initialize exception handlers (sub_12C0 / sub_4A88)
+  // Initialize exception handlers (InitializeCpuArch2 / InitExceptionHandlers)
   {
     UINT8   Enabled;
     UINT64  VectorInfo;
     UINT64  ExceptionStatus;
 
-    // Determine if cache is enabled (sub_243C)
+    // Determine if cache is enabled (MtrrReadDefaultType)
     Enabled = (GetRflags () & (1 << 9)) ? 1 : 0;
 
-    // Load GDT (sub_8EC0)
+    // Load GDT (ReadGdtr)
     // Loads the OS-visible GDT descriptor
 
-    // Get vector info from config table (sub_12C0)
+    // Get vector info from config table (InitializeCpuArch2)
     VectorInfo = 0;
     ExceptionStatus = InitExceptionHandlers (VectorInfo);
 
-    // Write back invalidate cache (sub_2460)
+    // Write back invalidate cache (WriteBackInvalidateCache)
     if (Enabled)
       __asm { wbinvd }
   }
@@ -1493,10 +1493,10 @@
   // Program GCD memory attributes based on current MTRR settings
   ProgramMemoryAttributes ();
 
-  // Program CPU features (sub_3048)
+  // Program CPU features (ProgramCpuFeatures)
   ProgramCpuFeatures ();
 
-  // Initialize MTRR sync (sub_1880)
+  // Initialize MTRR sync (MtrrSyncInit)
   MtrrSyncInit ();
 
   // Write back and invalidate cache
@@ -1506,7 +1506,7 @@
 }
 
 /**
-  Main initialization sequence (sub_9E0 at 0x9E0).
+  Main initialization sequence (DriverMainInit at 0x9E0).
 
   Executes the full driver initialization chain:
     UefiBootServicesTableLib -> UefiRuntimeServicesTableLib ->
@@ -1514,7 +1514,7 @@
     DxeServicesTableLib -> ProgramMemoryAttributes
     -> ProgramCpuFeatures -> MtrrSyncInit -> WBINVD
 
-  Calls sub_13A0 (CpuArchDxeMain) at the end.
+  Calls CpuArchDxeMain at the end.
 
   @param[in]  ImageHandle   EFI image handle.
   @param[in]  SystemTable   EFI system table.
@@ -1529,37 +1529,37 @@
 {
   UINT64 Status;
 
-  // 1. UefiBootServicesTableLibConstructor (sub_234C)
+  // 1. UefiBootServicesTableLibConstructor (UefiBootServicesLibCtor)
   Status = UefiBootServicesTableLibConstructor (ImageHandle, SystemTable);
   if (DebugEnabled () && Status) {
     DebugPrint (0x80000000, "\nASSERT_EFI_ERROR (Status = %r)\n", Status);
     DebugAssert (__FILE__, __LINE__, "!EFI_ERROR (Status)");
   }
 
-  // 2. UefiRuntimeServicesTableLibConstructor (sub_23C8)
+  // 2. UefiRuntimeServicesTableLibConstructor (UefiRuntimeServicesLibCtor)
   Status = UefiRuntimeServicesTableLibConstructor (ImageHandle, SystemTable);
   if (DebugEnabled () && Status) {
     DebugPrint (0x80000000, "\nASSERT_EFI_ERROR (Status = %r)\n", Status);
     DebugAssert (__FILE__, __LINE__, "!EFI_ERROR (Status)");
   }
 
-  // 3. UefiLibConstructor (sub_2A9C -- nop)
+  // 3. UefiLibConstructor (UefiLibConstructor -- nop)
   Status = 0;
 
-  // 4. DxeHobLibConstructor (sub_2BE8)
+  // 4. DxeHobLibConstructor (DxeHobLibCtor)
   Status = DxeHobLibConstructor (ImageHandle, SystemTable);
   if (DebugEnabled () && Status) {
     DebugPrint (0x80000000, "\nASSERT_EFI_ERROR (Status = %r)\n", Status);
     DebugAssert (__FILE__, __LINE__, "!EFI_ERROR (Status)");
   }
 
-  // 5. DxeServicesTableLibConstructor (sub_2BF8)
+  // 5. DxeServicesTableLibConstructor (InitializePciExpress)
   gMmPciBase = GetPciExpressBase ();
 
-  // 6. ProgramMemoryAttributes (sub_2C54)
+  // 6. ProgramMemoryAttributes (ResetColdSystem)
   Status = ResetColdSystem ();
 
-  // 7. DxeServicesTableLibConstructor2 (sub_4A00)
+  // 7. DxeServicesTableLibConstructor2 (DxeServicesLibCtor)
   Status = DxeServicesTableLibConstructor (ImageHandle, SystemTable);
   if (DebugEnabled () && Status) {
     DebugPrint (0x80000000, "\nASSERT_EFI_ERROR (Status = %r)\n", Status);
@@ -1599,17 +1599,17 @@
   // Process library constructor list
   DriverMainInit ((UINT64)ImageHandle, (UINT64)SystemTable);
 
-  // Call main entry wrapper (sub_DB0 -> sub_13A0)
+  // Call main entry wrapper (CpuArchDxeEntry -> CpuArchDxeMain)
   Status = CpuArchDxeMain ();
   if (Status) {
-    // On failure: process destructors (sub_DA0)
+    // On failure: process destructors (CpuArchDxeUnload)
   }
 
   return Status;
 }
 
 /*==========================================================================
- * CPU Feature Programming (sub_3048 at 0x3048)
+ * CPU Feature Programming (ProgramCpuFeatures at 0x3048)
  *==========================================================================*/
 
 /**
@@ -1659,7 +1659,7 @@
 
 /**
   Convert cache type to memory attribute mask.
-  (sub_1A60 at 0x1A60)
+  (CacheTypeToMemAttr at 0x1A60)
 
   @param[in]  CacheType   MTRR memory type:
       0 = UC -> returns 1   (EFI_MEMORY_UC)
@@ -1687,7 +1687,7 @@
 
 /**
   Find GCD memory map entries spanning a given address range.
-  (sub_1B70 at 0x1B70)
+  (FindMemMapEntry at 0x1B70)
 
   @param[in]  a1              GCD map descriptor array.
   @param[in]  i               Number of descriptor entries.
@@ -1737,7 +1737,7 @@
 /**
   Set memory space attributes via GCD, for a given range spanning
   GCD map entries.
-  (sub_1C80 at 0x1C80)
+  (SetMemAttrViaGcd at 0x1C80)
 
   @param[in]  a1              GCD descriptor array.
   @param[in]  i               GCD entry count.
@@ -1791,7 +1791,7 @@
 }
 
 /*==========================================================================
- * Program Memory Attributes (sub_1E40 at 0x1E40)
+ * Program Memory Attributes (ProgramMemoryAttributes at 0x1E40)
  *==========================================================================*/
 
 /**
@@ -1801,7 +1801,7 @@
   appropriate cache type attribute.  Merges adjacent ranges with
   the same cache type for efficient GCD programming.
 
-  (sub_1E40 at 0x1E40, ~0x50C bytes)
+  (ProgramMemoryAttributes at 0x1E40, ~0x50C bytes)
 **/
 UINT64
 ProgramMemoryAttributes (
@@ -1822,7 +1822,7 @@
   UINT64  Index;
   UINT64  k, jj;
 
-  // MP sync: sub_568C (1, 69639, 0, 0, 0)
+  // MP sync: MpSyncCall (1, 69639, 0, 0, 0)
   VarCount = GetEffectiveVariableMtrrCount ();
 
   gMtrrSyncLock = 1;
@@ -1864,7 +1864,7 @@
 
   // Process WB type entries (MTRR type 6)
   for (k = 0; k < VarCount; k++) {
-    // sub_1C80 for each WB region
+    // SetMemAttrViaGcd for each WB region
   }
 
   // Merge adjacent ranges with same cache type in fixed MTRR region
@@ -1906,12 +1906,12 @@
 }
 
 /*==========================================================================
- * Exception Handlers (sub_4A88 at 0x4A88, sub_4D3C at 0x4D3C)
+ * Exception Handlers (InitExceptionHandlers at 0x4A88, DispatchException at 0x4D3C)
  *==========================================================================*/
 
 /**
   Initialize CPU exception handlers.
-  (sub_4A88 at 0x4A88, from CpuExceptionHandlerLib DxeException.c)
+  (InitExceptionHandlers at 0x4A88, from CpuExceptionHandlerLib DxeException.c)
 
   Sets up:
     1. Reserved vector table (22528 bytes = 256 * 88-byte entries)
@@ -2023,7 +2023,7 @@
 
 /**
   Set IDT entry stub (patch MOV byte with vector number).
-  (sub_858 at 0x858)
+  (SetIdtEntry at 0x858)
 
   @param[in]  IdtTable     IDT table address.
   @param[in]  Vector       Vector number (0-255).
@@ -2042,7 +2042,7 @@
 
 /**
   Get exception stub template info (exception stub header size).
-  (sub_834 at 0x834)
+  (GetExceptionTemplateInfo at 0x834)
 
   Fills in template info: default stub header size = 16 bytes.
 
@@ -2062,7 +2062,7 @@
 }
 
 /**
-  Install and setup IDT entries (sub_4FA4 at 0x4FA4).
+  Install and setup IDT entries (SetupIdtTable at 0x4FA4).
 
   @param[in]  IdtTable   IDT table address.
   @param[in]  EntryCode  Pointer to interrupt entry code array.
@@ -2112,7 +2112,7 @@
 
 /**
   Initialize external interrupt handler table notification.
-  (sub_6A70 equivalent)
+  (InitializeExternalInterruptHandlerTable equivalent)
 **/
 VOID
 InitializeExternalInterruptHandlerTable (
@@ -2125,12 +2125,12 @@
 }
 
 /*==========================================================================
- * Spin Lock operations (sub_6A70, sub_6AA4, sub_6B20)
+ * Spin Lock operations (AcquireSpinLock, TryAcquireSpinLock, ReleaseSpinLock)
  *==========================================================================*/
 
 /**
   Acquire spin lock (set to 2, blocking).
-  (sub_6A70 at 0x6A70)
+  (AcquireSpinLock at 0x6A70)
 
   Sets spin lock to initial value 1 (released state, acquire intent).
 
@@ -2149,7 +2149,7 @@
 
 /**
   Try to acquire spin lock (atomic compare-exchange).
-  (sub_6AA4 at 0x6AA4)
+  (TryAcquireSpinLock at 0x6AA4)
 
   @param[in]  Lock   Pointer to spin lock variable.
 
@@ -2186,7 +2186,7 @@
 
 /**
   Release spin lock (set back to 1).
-  (sub_6B20 at 0x6B20)
+  (ReleaseSpinLock at 0x6B20)
 
   @param[in]  Lock   Pointer to spin lock variable.
 **/
@@ -2209,7 +2209,7 @@
 }
 
 /*==========================================================================
- * MTRR Sync Init (sub_1880 at 0x1880, MtrrSync.c)
+ * MTRR Sync Init (MtrrSyncInit at 0x1880, MtrrSync.c)
  *==========================================================================*/
 
 /**
@@ -2230,7 +2230,7 @@
   // Allocate MTRR sync buffer (608 = 0x260 bytes)
   gMtrrBuffer = AllocateZeroedPages (0x260);
 
-  // Register protocol notify (sub_29F8)
+  // Register protocol notify (RegisterMtrrNotify)
   // gBS->RegisterProtocolNotify with MP services protocol
   Status = RegisterMtrrNotify (155, gMtrrBuffer);
   if (DebugEnabled () && Status) {
@@ -2243,7 +2243,7 @@
 
 /**
   Register MTRR protocol notify.
-  (sub_29F8 at 0x29F8)
+  (RegisterMtrrNotify at 0x29F8)
 
   @param[in]  n155         Protocol GUID index.
   @param[in]  SystemTable  MTRR buffer pointer.
@@ -2267,7 +2267,7 @@
 
 /**
   Get PCD protocol instance.
-  (sub_296C at 0x296C)
+  (GetPcdProtocol at 0x296C)
 
   @param[in]  ImageHandle   Protocol GUID index.
   @param[in]  SystemTable   System Table.
@@ -2300,12 +2300,12 @@
 }
 
 /*==========================================================================
- * PEI HOB List (sub_2B64 at 0x2B64, DxeHobLib.c)
+ * PEI HOB List (DxeHobLibConstructor at 0x2B64, DxeHobLib.c)
  *==========================================================================*/
 
 /**
   Get HOB list via config table lookup.
-  (sub_2B64 at 0x2B64)
+  (DxeHobLibConstructor at 0x2B64)
 
   @param[in]  ImageHandle  Image handle.
   @param[in]  SystemTable  System Table.
@@ -2335,12 +2335,12 @@
 }
 
 /*==========================================================================
- * PCI Express Init (sub_2BF8 at 0x2BF8, sub_2C18 at 0x2C18)
+ * PCI Express Init (GetPciExpressBase at 0x2BF8, PciExpressLibAddress at 0x2C18)
  *==========================================================================*/
 
 /**
   Initialize PCI Express MMIO base address.
-  (sub_2BF8 at 0x2BF8)
+  (GetPciExpressBase at 0x2BF8)
 
   Reads the PCD for PciExpressBaseAddress.
 
@@ -2364,7 +2364,7 @@
 
 /**
   Translate PCI Express config address to MMIO address.
-  (sub_2C18 at 0x2C18)
+  (PciExpressLibAddress at 0x2C18)
 
   @param[in]  Address  PCIe config space address (bits 27:0).
 
@@ -2382,7 +2382,7 @@
 }
 
 /*==========================================================================
- * Reset + CMOS (sub_2C54 at 0x2C54)
+ * Reset + CMOS (ResetColdSystem at 0x2C54)
  *==========================================================================*/
 
 /**
@@ -2447,12 +2447,12 @@
 }
 
 /*==========================================================================
- * WBINVD / WriteBackInvalidateCache (sub_243C, sub_2460 at 0x2460)
+ * WBINVD / WriteBackInvalidateCache (MtrrReadDefaultType, WriteBackInvalidateCache at 0x2460)
  *==========================================================================*/
 
 /**
   Read MTRR default type from MSR 0x2FF (IA32_MTRR_DEF_TYPE), bits 7:0.
-  (sub_243C at 0x243C)
+  (MtrrReadDefaultType at 0x243C)
 
   Also checks if cache was enabled via RFLAGS.IF before disabling.
 
@@ -2475,7 +2475,7 @@
 
 /**
   Write back and invalidate cache (WBINVD).
-  (sub_2460 at 0x2460)
+  (WriteBackInvalidateCache at 0x2460)
 
   @param[in]  CacheType  0 = execute WBINVD with interrupts disabled.
 **/
@@ -2494,12 +2494,12 @@
 }
 
 /*==========================================================================
- * APIC Helpers (sub_2E3C, sub_2E78, sub_2ECC, sub_2F30, sub_2F8C)
+ * APIC Helpers (IsX2Apic, GetApicBase, ReadLocalApicReg, WriteLocalApicReg, GetApicMode, GetApicId)
  *==========================================================================*/
 
 /**
   Detect if system is using x2APIC mode.
-  (sub_2DF8 at 0x2DF8)
+  (IsX2Apic at 0x2DF8)
 
   @return 1 if x2APIC is enabled, 0 if xAPIC.
 **/
@@ -2536,7 +2536,7 @@
 
 /**
   Read local APIC register.
-  (sub_2E78 at 0x2E78, BaseXApicX2ApicLib.c)
+  (ReadLocalApicReg at 0x2E78, BaseXApicX2ApicLib.c)
 
   @param[in]  MmioOffset  APIC register offset from base.
 
@@ -2561,7 +2561,7 @@
 
 /**
   Write local APIC register.
-  (sub_2ECC at 0x2ECC)
+  (WriteLocalApicReg at 0x2ECC)
 
   @param[in]  MmioOffset  APIC register offset from base.
   @param[in]  Value       32-bit value to write.
@@ -2590,7 +2590,7 @@
 
 /**
   Get APIC mode (1 = xAPIC, 2 = x2APIC).
-  (sub_2F30 at 0x2F30)
+  (GetApicMode at 0x2F30)
 
   @return APIC mode (1 = xAPIC, 2 = x2APIC).
 **/
@@ -2615,7 +2615,7 @@
 
 /**
   Get local APIC ID.
-  (sub_2F8C at 0x2F8C)
+  (GetApicId at 0x2F8C)
 
   @return Local APIC ID (0-255).
 **/
@@ -2649,4 +2649,4 @@
 volatile UINT32    gFixedMtrrTable[33] = { 0 };
 
 /// gVariableMtrrCountOffset: Difference between MTRRCAP VCNT and available.
-volatile UINT32    gVariableMtrrCountOffset = 0;  // dword_8DE0
\ No newline at end of file
+volatile UINT32    gVariableMtrrCountOffset = 0;  // dword_8DE0
diff --git a/UefiCpuPkg/CpuArchDxe/CpuArchDxe.h b/UefiCpuPkg/CpuArchDxe/CpuArchDxe.h
index caed1c4..730eb14 100644
--- a/UefiCpuPkg/CpuArchDxe/CpuArchDxe.h
+++ b/UefiCpuPkg/CpuArchDxe/CpuArchDxe.h
@@ -611,7 +611,7 @@
 
 EFI_STATUS
 EFIAPI
-in sub_1E40 to iterate through fixed MTRR ranges(
+iterate through fixed MTRR ranges(
   VOID
 );
 
@@ -623,7 +623,7 @@
 
 EFI_STATUS
 EFIAPI
-by sub_61F to determine the correct save slot index.(
+used to determine the correct save slot index.(
   VOID
 );
 
@@ -786,7 +786,7 @@
 
 EFI_STATUS
 EFIAPI
-global services (sub_55DC equivalent)(
+global services (SaveGlobalServices equivalent)(
   VOID
 );
 
@@ -798,25 +798,25 @@
 
 EFI_STATUS
 EFIAPI
-FPU + SSE (sub_410)(
+FPU + SSE (InitializeFpu equivalent)(
   VOID
 );
 
 EFI_STATUS
 EFIAPI
-exception handlers (sub_12C0 / sub_4A88)(
+exception handlers (InitializeCpuArch2 / InitExceptionHandlers)(
   VOID
 );
 
 EFI_STATUS
 EFIAPI
-if cache is enabled (sub_243C)(
+if cache is enabled (MtrrReadDefaultType)(
   VOID
 );
 
 EFI_STATUS
 EFIAPI
-GDT (sub_8EC0)(
+GDT (ReadGdtr)(
   VOID
 );
 
@@ -828,13 +828,13 @@
 
 EFI_STATUS
 EFIAPI
-vector info from config table (sub_12C0)(
+vector info from config table (InitializeCpuArch2)(
   VOID
 );
 
 EFI_STATUS
 EFIAPI
-back invalidate cache (sub_2460)(
+back invalidate cache (WriteBackInvalidateCache)(
   VOID
 );
 
@@ -858,13 +858,13 @@
 
 EFI_STATUS
 EFIAPI
-CPU features (sub_3048)(
+CPU features (ProgramCpuFeatures)(
   VOID
 );
 
 EFI_STATUS
 EFIAPI
-MTRR sync (sub_1880)(
+MTRR sync (MtrrSyncInit)(
   VOID
 );
 
@@ -888,13 +888,13 @@
 
 EFI_STATUS
 EFIAPI
-main entry wrapper (sub_DB0 -> sub_13A0)(
+main entry wrapper (CpuArchDxeEntry -> CpuArchDxeMain)(
   VOID
 );
 
 EFI_STATUS
 EFIAPI
-failure: process destructors (sub_DA0)(
+failure: process destructors (CpuArchDxeUnload)(
   VOID
 );
 
@@ -950,7 +950,7 @@
 
 EFI_STATUS
 EFIAPI
-sync: sub_568C (1, 69639, 0, 0, 0)(
+sync: MpSyncCall (1, 69639, 0, 0, 0)(
   VOID
 );
 
@@ -1178,7 +1178,7 @@
 
 EFI_STATUS
 EFIAPI
-protocol notify (sub_29F8)(
+protocol notify (RegisterMtrrNotify)(
   VOID
 );
 
@@ -1286,4 +1286,4 @@
   VOID
 );
 
-#endif /* __CPUARCHDXE_H__ */
\ No newline at end of file
+#endif /* __CPUARCHDXE_H__ */