# SBPEI

| Field       | Value                                      |
|-------------|--------------------------------------------|
| Index       | 396                                        |
| Module      | SBPEI                                      |
| Size        | 4,388 bytes (1124h)                        |
| Phase       | PEI                                        |
| SHA256      | 1d4aa177f21a7331a11b7af2821ef57eef0426517e8fa0348466c6e957aedfbd |
| Functions   | 26                                         |

## Overview

SBPEI is a PEI driver from AmiCRBPkg/Chipset/SB that initializes Southbridge (SB) hardware during the PEI phase. It detects the chipset revision, configures SATA controllers, manages platform-specific IO ports, and installs the SB PEI protocol. It performs CMOS-based revision detection and SATA controller bus master enable.

## Key Functions

- **ModuleEntryPoint** -- Main entry; allocates SB config buffer, installs SB PPI protocol
- **sub_FFE2FD3A** -- Southbridge revision detection via CMOS (index 0x70/0x71) and PCI config space
- **sub_FFE2FE7D** -- SATA controller initialization; decodes SB PCI bus/device/function, enables bus master
- **sub_FFE30177 / sub_FFE3027F** -- Memory-mapped register MMIO allocation and address translation
- **sub_FFE300DB / sub_FFE300EA / sub_FFE3016B** -- PCD service wrappers for PcdPciExpressBaseAddress and PcdPciExpressBasePort
- **sub_FFE2FF1C / sub_FFE2FF4C / sub_FFE2FF7A** -- I/O port read/write with alignment assertion

## Dependencies

- PiPei, Uefi base libraries
- PCD PPI (PeiPcdLib)
- I/O port access (IoLib)
- PCI configuration read/write
- CMOS access for chipset revision detection
- PEI Services Table Pointer Library (IDT-based)

## Platform

- **Architecture**: IA-32 (x86)
- **Subsystem**: EFI_BOOT_SERVICE_DRIVER (0x0B)
- **Source**: AmiCRBPkg/Chipset/SB/SBPEI.c
- **Linker**: MSVS 2015