# PcieErrorHandler
**Index:** 0224 | **Size:** 50,656 bytes (202,624 body) | **Phase:** SMM

## Overview
SMM PCI Express error handler for the Intel Purley platform. Manages PCIe Advanced Error Reporting (AER), PCIe component/device error detection and logging, and root port error handling. Initializes through AutoGen library constructors then registers SMM error handling callbacks for PCIe bus error events. Interfaces with the platform RAS infrastructure to log PCIe errors and communicate with BMC.

## Key Functions
- **ModuleEntryPoint** -- SMM entry point: initializes PCIe handlers with recovered entry-flow helpers.
- **PcieErrorHandlerInitLibraries** (recovered from `sub_7958`) -- Library constructor chain initialization (`gST`, `gBS`, `gRT`, `gSmst`).
- **RegisterPcieErrorHandler** (recovered from `sub_7E70`) -- Main initialization: locates PCIe-related protocols and registers SMI handlers.
- **PcieErrorHandlerInitFailure** (recovered from `sub_7E00`) -- Fallback/cleanup handler on initialization failure.

## Recovered Symbol Mapping
- `sub_7958` -> `PcieErrorHandlerInitLibraries`
- `sub_7E70` -> `RegisterPcieErrorHandler`
- `sub_7E00` -> `PcieErrorHandlerInitFailure`

## Protocols/Dependencies
- UEFI Boot Services, Runtime Services, SMM System Table (gSmst)
- EFI_SMM_BASE2_PROTOCOL, EFI_SMM_SW_DISPATCH2_PROTOCOL
- IIO Protocol, MM PCI Base Protocol for PCIe config space access

## Platform
Intel Purley (Skylake-SP Xeon), HR650X
Source: PurleyPlatPkg/Ras/Smm/ErrHandling/PcieErrorHandler/