# CpuIoPei
**Index:** 0408 | **Size:** 5,280 bytes | **Phase:** PEI | **Format:** PE32 (Ia32)

## Overview
CPU I/O PEIM providing the EFI_PEI_CPU_IO_PPI interface for port I/O, MMIO, and memory-mapped I/O access during the PEI phase. Implements byte/word/dword port I/O read/write with string variants, MMIO access (word/dword/qword), and unaligned memory read/write helpers (16/32/64-bit). Validates I/O port alignment and invokes x86 assembly I/O instructions.

## Key Functions
- **IoReadBufferFx / IoReadPortWordString / IoReadPortDwordString** -- Port I/O string read (byte/word/dword)
- **IoWriteBufferByte / IoWritePortWordString / IoWritePortDwordString** -- Port I/O string write (byte/word/dword)
- **IoReadPortWord / IoWritePortWord** -- Single port I/O word operations
- **IoReadPortDword / IoWritePortDword** -- Single port I/O dword operations
- **IoReadMmioWord / IoWriteMmioWord / IoReadMmioQword / IoWriteMmioQword** -- MMIO read/write
- **ReadUnaligned16 / WriteUnaligned16 / ReadUnaligned32 / WriteUnaligned32 / ReadUnaligned64** -- Unaligned memory access with DEBUG asserts
- **GetPeiServicesTable** -- PEI services table pointer retrieval
- **GetDebugInstance** -- Debug PPI locator for ASSERT messages
- **SetMem / SetMem32 / SetMem32Fill / CopyMem** -- Memory utility wrappers

## Dependencies
- EFI_PEI_CPU_IO_PPI -- CPU I/O PPI interface
- x86 IN/OUT instruction family (in/out byte/word/dword, string variants)
- MMIO address space
- Debug Library PPI (for unaligned access asserts)

## Platform
Intel Purley (Skylake-SP Xeon), HR650X
Source: UefiCpuPkg/CpuIoPei/CpuIoPei.c