# CpuMpPei
**Index:** 0401 | **Size:** 33,696 bytes | **Phase:** PEI | **Format:** PE32 (Ia32)

## Overview
Multi-processor (MP) initialization and management PEIM for the PEI phase. Provides exception handling, CPU synchronization primitives (pause, sfence, deep sleep), MSR and cpuid access, MP safe buffer copy, BIST (Built-In Self-Test) collection, and floating-point unit initialization. Dispatches CPU MP services and manages processor-specific data structures across all logical processors.

## Key Functions
- **CpuMpPeiInit** -- Module entry: initializes MP services, registers CPU MP PPI
- **ExceptionContextSwitch** -- Core exception dispatcher with nested exception support, saves/restores CPU context across IDT/GDT boundaries
- **AsmExceptionEntryDiv0 / AsmExceptionEntry0** -- Assembly exception stubs for divide error and general exceptions
- **InitializeFloatingPointUnits** -- FPU/SSE initialization for each AP
- **MpSafeCopyBuffer** -- Safe inter-processor buffer copy with TLB management
- **CpuBistCollect** -- Collects BIST results from all processors
- **CpuPause / CpuSfence / CpuDeepSleep** -- Low-level CPU synchronization and power management
- **AsmReadMsr64 / AsmWriteMsr64 / AsmCpuid** -- MSR and CPUID access wrappers
- **HobListRead / PpiLocate / PpiFindByGuid** -- PEI service helpers for HOB and PPI traversal
- **DebugPrint / DebugAssert** -- Debug logging via GET_DEBUG_SERVICE PPI

## Dependencies
- EFI_PEI_CPU_MP_PPI -- CPU multi-processor PPI interface
- EFI_PEI_SERVICES -- PEI service table (PPI locator, HOB management)
- GET_DEBUG_SERVICE PPI -- Debug output infrastructure
- IDT/GDT -- Interrupt and global descriptor tables

## Platform
Intel Purley (Skylake-SP Xeon), HR650X
Source: UefiCpuPkg/CpuMpPei/