# MeUma

## Function Table

| Address | Name | Description |
|---------|------|-------------|
|  | **ModuleEntryPoint** |  |
|  | **ReadUnaligned64** |  |
|  | **WriteUnaligned64** |  |
|  | **IoRead16** |  |
|  | **IoWrite16** |  |
|  | **IoRead32** |  |
|  | **ReadPciCfg16** |  |
|  | **PcdGet32** |  |
|  | **PcdGetSize** |  |
|  | **CompareGuid** |  |
|  | **ValidateUmaLocation** |  |
|  | **GetOnBoardMeType** |  |
|  | **GetMeFs1FromHob** |  |
|  | **GetPeiPerformance** |  |
|  | **FindPerformanceLogIndex** |  |
|  | **IsHeciSkipped** |  |
|  | **SendHeciMessage** |  |
|  | **MicroDelay** |  |
| Globals | **// ---------------------------------------------------------------------------** |  |
| The | **PPI descriptor (GUID + EFI_PEI_PPI_DESCRIPTOR) for the ME UMA PPI.** |  |
| Located | **in the .data section at 0xffda3390.** |  |
| extern | **EFI_GUID  gMeUmaPpiGuid;** |  |
| The | **actual ME_UMA_PPI structure** |  |
| Flags | **/ state byte at 0xffda339c** |  |
| Function | **prototypes** |  |
| Internal | **functions (previously sub_*)** |  |
| The | **actual read goes through the memory-mapped ECAM or I/O CFG mechanism.** |  |
| We | **construct the address and decode it via the PCI Express library.** |  |
| UINTN | **Address = (PciCfg.Reg | 0) & 0xFFF;  // simplified: see PciExpressLib** |  |
| Internal | **Helpers** |  |
| points | **to Hob + 24** |  |
| UMA | **Parameter Validation** |  |
| Check | **if the ME is in a debug or error mode that skips UMA checking.** |  |
| if | **(!(UINT8)ModuleEntryPoint (NULL, NULL)) {** |  |
| Calculate | **UMA size:** |  |
| MeUmaSize | **= (MeNcMemLowLimit & 0xFFF80000) + 0x80000 - MeNcMemLowBaseAddr** |  |
| MeUmaSize | **+= MeNcMemHighLimit** |  |
| MeUmaSize | **= (MeNcMemLowLimit & 0xFFF80000) + 0x80000 - MeNcMemLowBaseAddr;** |  |
| Read | **the UMA parameters from Silicon registers (via PCI config access).** |  |
| UmaBase | **= *(UINT32 *)((UINTN)PciCfgRead (0) + 240);  // offset 0xF0** |  |
| offset | **0xF4** |  |
| If | **base addresses are zero, skip validation.** |  |
| if | **(MeNcMemLowBaseAddr == 0 || MeNcMemLowLimit == 0) {** |  |
| Validate | **the UMA base addresses match Silicon registers.** |  |
| if | **(MeNcMemLowBaseAddr != UmaBase || MeNcMemHighBaseAddr != UmaBaseExt) {** |  |
| Validate | **UMA size: must not exceed 64 MB, must be even (2 MB aligned).** |  |
| if | **(MeUmaSizeCalc >> 20 > 64) {** |  |
| ME | **Type Detection** |  |
| Check | **Debug Mode via PCH PMC (DWR flow).** |  |
| if | **(IsPchDwrFlow ()) {** |  |
| 15 | **}** |  |
| Read | **the ME Firmware Status (MEFS) register from PCI config.** |  |
| MeFirmwareStatus | **= *(UINT32 *)((UINTN)PciCfgRead (0) + 64);  // offset 0x40** |  |
| Fall | **back to HOB if MEFS is invalid.** |  |
| MeFirmwareStatus | **= GetMeFs1FromHob ();** |  |
| Evaluate | **the ME type from the status.** |  |
| if | **((MeFirmwareStatus & 0xF) == 0xF) {** |  |
| Unknown | **type** |  |
| 2 | **case 2:** |  |
| 1 | **default:** |  |
| Could | **not read HOB, use fallback path.** |  |
| DEBUG | **((EFI_D_ERROR, "HECI: GetMeFs1FromHob() Can't read correctly MeFwHob info\n"));** |  |
| Performance | **Logging (PEI Performance)** |  |
| Use | **existing HOB data.** |  |
| Build | **fresh HOBs for the performance log and ID array.** |  |
| HECI | **Message / PPI Installation** |  |
| Entry | **Point** |  |
| if | **((IoRead32 (1024068) & 0x80) == 0) {** |  |
| Check | **if the system has valid ME firmware (skip on debug/error).** |  |
| byte_FFDA339C | **= (IsHeciSkipped () < 0) ? 0 : byte_FFDA339C;** |  |
| Install | **the ME UMA PPI.** |  |
| PeiServices | **= GetPeiServices ();** |  |

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*Generated by HR650X BIOS Decompilation Project*