# OemReadyToBootDxe

- **Index:** 0102
- **PE File:** OemReadyToBootDxe.efi
- **Size:** 4,640 bytes (0x1220)
- **SHA256:** fcf4696c02b02555f2e2698a03f78b3b67d4bfbda82b0cf056e26e201ec592d8
- **Phase:** DXE (Driver Execution Environment)
- **Source:** LenovoServerPkg/OemReadyToBootDxe

## Overview

OemReadyToBootDxe registers a ReadyToBoot event callback that clears NVMe power fault status on all CPU sockets just before the OS boot loader is invoked. It locates the IIO UDS (IIO Unified Data Structure) and CPU CSR Access protocols, reads the CPUBUSNO registers for each present socket, and scans the 4 NVMe ports per socket. For each NVMe port, it reads the port status register at PCI offset 0xAA and clears bit 1 (power fault) by writing a 1 to it (write-1-to-clear). This ensures that any transient power fault conditions detected during POST do not persist into the OS, preventing potential NVMe device enumeration failures.

## Key Functions

| Function | Address | Purpose |
|----------|---------|---------|
| ModuleEntryPoint | 0x350 | UEFI entry point; initializes globals, caches HOB list, reads PciExpressBaseAddress from PCD, calls OemReadyToBootDxeEntry |
| OemReadyToBootDxeEntry | 0x4A0 | Creates ReadyToBoot event with ClearNvmePowerFaultStatus as the notification function |
| ClearNvmePowerFaultStatus | 0x400 | Locates IIO UDS and CPU CSR access protocols; reads CPUBUSNO per socket; calls IioScanNvmePort |
| IioScanNvmePort | 0x350 | Scans 4 NVMe ports on a given socket; reads status at PCI offset 0xAA; clears bit 1 (power fault) |
| PciExpressRead | 0x460 | Translates PCIe register address to MMIO address using cached base address |
| GetHobList | 0x4C0 | Retrieves HOB list from system table configuration table |
| GetPcdProtocol | 0x550 | Lazily locates and caches the PCD protocol |

## Protocols/Dependencies

- **EFI_IIO_UDS_PROTOCOL** -- IIO UDS for socket presence detection (bit 1 of byte 2067)
- **EFI_CPU_CSR_ACCESS_PROTOCOL** -- CPU CSR register read for CPUBUSNO (register 0x13023A0C)
- **PCD_PROTOCOL** -- PCIe MMIO base address (PCD token 5)
- **EFI_BOOT_SERVICES** -- Protocol location, event creation (CreateEventEx with ReadyToBoot GUID)

## Platform

HR650X (Lenovo ThinkSystem) -- X64 UEFI DXE driver. Supports up to 2 CPU sockets (Socket 0 always present, Socket 1 conditional on IIO UDS bit). Original source copyright Inspur Corporation with SPDX BSD-2-Clause-Patent license.