# PciBus

## Function Table

| Address | Name | Description |
|---------|------|-------------|
|  | **PciBusEntryPoint** |  |
|  | **ProcessDriverInit** |  |
|  | **PciBusDriverBindingSupported** |  |
|  | **PciBusDriverBindingStart** |  |
|  | **PciBusDriverBindingStop** |  |
|  | **PciBusEnumerateBus** |  |
|  | **PciBusEnumerateDevice** |  |
|  | **PciBusInitDevice** |  |
|  | **PciBusParseBar** |  |
|  | **PciBusParseExpBar** |  |
|  | **PciBusCalculateBrgResources** |  |
|  | **PciBusOptimizeBrgResources** |  |
|  | **PciBusArrangeFixResources** |  |
|  | **PciBusAllocateResource** |  |
|  | **PcieSetLinkProperties** |  |
|  | **PcieSetDeviceProperties** |  |
|  | **PcieInitLink** |  |
|  | **PcieLinkTraining** |  |
|  | **PcieCollectCaps** |  |
|  | **PcieSetAspm** |  |
|  | **Pcie2SetLinkProperties** |  |
|  | **Pcie2SetDeviceProperties** |  |
|  | **SriovProbeDevice** |  |
|  | **PciBusInstallPciIo** |  |
|  | **PciBusProcessRomImage** |  |
|  | **PciBusS3BootScriptSave** |  |
|  | **PciBusS3BootScriptExecute** |  |
|  | **PciBusAllocateDmaBuffer** |  |
|  | **PciBusDebugPrint** |  |
|  | **PciBusAssertReport** |  |
|  | **PciBusFindGuidInHob** |  |
|  | **PciBusPciExpressAddr** |  |
|  | **PciBusGetNextFunction** |  |
|  | **PciBusIsPciDevicePresent** |  |
|  | **PciBusSkipNicBySlot** |  |
|  | **PciBusCheckNicDriverBinding** |  |
| Libraries | **used:** |  |
| AmiPciExpressLib | **(e:\hs\AmiModulePkg\Library\AmiPciExpressLib)** |  |
| AmiSriovLib | **(e:\hs\AmiModulePkg\Library\AmiSriovLib)** |  |
| AmiPciBusLib | **(e:\hs\AmiModulePkg\Library\AmiPciBusLib)** |  |
| SbPciHotPlugLib | **(e:\hs\AmiCRBPkg\Chipset\SB\SbPciHotPlugLib)** |  |
| Module | **layout:** |  |
| 0x0002C0 | **- 0x001DCC: Driver Entry, Protocol Registration** |  |
| 0x001DCC | **- 0x00599C: Device Enumeration, Bridge Setup** |  |
| 0x00599C | **- 0x00B944: BAR Handling, SDL, Resource Allocation** |  |
| 0x00B944 | **- 0x00E5E0: Bus Scan, PciIo Installation, Option ROM** |  |
| 0x00E5E0 | **- 0x010C10: Option ROM, Platform Policy, Reset** |  |
| 0x010C10 | **- 0x018B58: PCI Express (Gen2/Gen3/Gen4 Link & Device Config)** |  |
| 0x018B58 | **- 0x01A84C: PciInitProtocol, IOMMU/DMA** |  |
| 0x01A84C | **- 0x01D0E0: S3 Boot Script** |  |
| 0x01D1A0 | **- 0x024B00: String table (.rdata)** |  |
| DRIVER | **ENTRY POINT** |  |
| Calls | **ProcessDriverInit() for DXE protocol init** |  |
| Calls | **PciBusDriverBindingSupported() to install driver binding** |  |
| Calls | **PciBusUnload() on failure** |  |
| PROCESSOR | **INITIALIZATION** |  |
| Stores | **gImageHandle, gST, gBS, gRT** |  |
| Calls | **PciBusInitDmaProtection()** |  |
| Configures | **CPU flags, cache control** |  |
| Waits | **for APs to finish initialization** |  |
| DRIVER | **BINDING PROTOCOL** |  |
| Validates | **PCI root bridge I/O protocol on controller** |  |
| Checks | **for ACPI device path** |  |
| Discovers | **cache line size from CPU info HOB** |  |
| Installs | **PciRootBridgeIo protocol** |  |
| Initializes | **root bridge instance** |  |
| Calls | **PciBusEnumerateBus() to scan devices** |  |
| Stops | **and uninstalls protocols for all child devices** |  |
| BUS | **ENUMERATION** |  |
| Scans | **all PCI buses starting from bus 0** |  |
| Discovers | **PCI devices and bridges** |  |
| Assigns | **bus numbers to bridges (Bus OOR = Out Of Range handling)** |  |
| Calls | **PciBusEnumerateDevice() for each discovered device** |  |
| Installs | **gEfiPciEnumerationCompleteProtocolGuid at end** |  |
| Reads | **VID/DID, checks vendor/device presence** |  |
| Calls | **PciBusCreatePciDeviceNode() to allocate device struct** |  |
| Calls | **PciBusGetPciDeviceData() to read config space** |  |
| Calls | **PciBusGetDeviceCapability() to parse capabilities** |  |
| Calls | **PciBusLocateSdlData() for SDL slot mapping** |  |
| Calls | **PciBusProbeDeviceBar() to read BARs** |  |
| Reports | **discovered device via PciBusReportDevice()** |  |
| Overrides | **device attributes from SDL configuration** |  |
| Sets | **PCI attributes via PciBusPciRead/PciBusPciWrite** |  |
| Handles | **device-specific initialization phases** |  |
| BAR | **HANDLING** |  |
| Iterates | **through 6 standard PCI BARs** |  |
| Determines | **BAR type (IO, MMIO32, MMIO64, PMEM32, PMEM64)** |  |
| Calculates | **BAR size and alignment** |  |
| Handles | **64-bit BARs spanning two registers** |  |
| Parses | **Extended BARs (PCI Express capability)** |  |
| Handles | **>4GB MMIO BARs** |  |
| RESOURCE | **ALLOCATION** |  |
| Calculates | **resource requirements per bridge** |  |
| Processes | **IO, MMIO32, MMIO64, PMEM32, PMEM64 per bridge** |  |
| Calls | **PciBusSortBridgeResources() for ordering** |  |
| Calls | **PciBusOptimizeBrgResources() for bridge resource optimization** |  |
| Calls | **PciBusInsertSortedBar() for sorted resource insertion** |  |
| Optimizes | **bridge resource windows** |  |
| Sorts | **device and bridge BARs by type** |  |
| Merges | **adjacent resources when possible** |  |
| Handles | **FIXED resources (pre-assigned by platform)** |  |
| Validates | **alignment (IO min 4K, MMIO min 1MB)** |  |
| Processes | **fixed bridge resource requirements** |  |
| Allocates | **IO and memory space to all bridges** |  |
| Handles | **non-contiguous resource allocation** |  |
| Uses | **AllocateIoSpace / AllocateMemorySpace primitives** |  |
| Probes | **each PCI device for resource requirements** |  |
| Prints | **"Probing PCI Device" + current resource state** |  |
| PCI | **EXPRESS LINK TRAINING & CONFIGURATION (Gen1/Gen2/Gen3/Gen4)** |  |
| Configures | **PCIe link capabilities via LINK_CAP/LINK_CTRL2** |  |
| Reads | **LNK_CNT register and applies settings** |  |
| Updates | **link control register with new values** |  |
| Displays | **LNK_CNT field breakdown:** |  |
| BwI | **(Bandwidth Init), BwMI, AuWi (Auto Width), CkPM, ExS (Extended Sync)** |  |
| CCk | **(Clock Common), Rtr (Retrain), LDis (Link Disable)** |  |
| RCB | **(Read Completion Boundary), ASPM** |  |
| Configures | **PCIe device capabilities (MaxPayload, MRRS, etc.)** |  |
| Reads | **DEV_CNT register, applies new settings** |  |
| Extended | **Tag, MaxPayload, Relaxed Ordering** |  |
| Displays | **DEV_CNT field breakdown** |  |
| Initializes | **link for downstream ports** |  |
| Handles | **ARI (Alternative Routing ID) configuration** |  |
| Gen2 | **enable/disable based on platform policy** |  |
| Disables | **link as needed** |  |
| Performs | **PCIe link training (recovery state handling)** |  |
| Configurable | **timeout per retry** |  |
| Reports | **EQ_STS (equalization status)** |  |
| Disables | **link on training failure** |  |
| Collects | **and displays all PCIe capabilities:** |  |
| PCIE_CAP | **(capability version, port type, slot)** |  |
| DEV_CAP | **(device capabilities including R2, FR, PowerS, etc.)** |  |
| LNK_CAP | **(link capabilities: speed, width, ASPM)** |  |
| SLT_CAP | **(slot capabilities)** |  |
| ROOT_CAP | **(root complex capabilities)** |  |
| Configures | **ASPM (Active State Power Management)** |  |
| Compares | **upstream/downstream port latency** |  |
| Respects | **PCI_SETUP_DONT_TOUCH for ASPM** |  |
| Calculates | **best ASPM state for the link** |  |
| Reads | **LNK_CNT2 register (CmDe, CmSOS, ECm, TrM, ...)** |  |
| Applies | **Gen2 link settings** |  |
| Configures | **DEV_CNT2 (EEPrB, LTR, IDO, ARI, Completion Timeout)** |  |
| Detects | **SR-IOV capable devices** |  |
| Reads | **ARI capability, page size** |  |
| Enumerates | **Virtual Functions (VFs)** |  |
| Updates | **mMaxBusFound after VF enumeration** |  |
| OPTION | **ROM** |  |
| Installs | **EFI_PCI_IO_PROTOCOL on device handle** |  |
| Configures | **OpROM enable/disable** |  |
| Loads | **and dispatches Option ROM images** |  |
| Handles | **OEM program devices** |  |
| Installs | **BusOvr (Bus Override) and LoadFile2 protocols** |  |
| Overrides | **ROM file location from SDL data** |  |
| Loads | **ROM image from specified location** |  |
| S3 | **BOOT SCRIPT SUPPORT** |  |
| Saves | **PCI configuration to S3 boot script** |  |
| Stores | **IO, memory, PCI CFG operations for S3 resume** |  |
| Executes | **S3 boot script entries** |  |
| Processes | **label, IO write, mem write, PCI CFG write operations** |  |
| Supports | **dispatch entries for early S3 restore** |  |
| Allocates | **DMA-safe buffer via IoMmu protocol** |  |
| Handles | **DMA remap attributes** |  |
| GPIO | **/ PLATFORM** |  |
| GPIO | **group/pin error strings indicate platform-specific GPIO configuration** |  |
| PCH | **LPC device ID validation for chipset SKU detection** |  |
| UTILITY | **FUNCTIONS** |  |
| Wrapper | **around DebugPrint()** |  |
| ErrorLevel | **mask controls output (0x400000=info, 0x80000000=error)** |  |
| Reports | **assertion failures** |  |
| References | **file:line triple from UEFI debug infrastructure** |  |
| Wraps | **GetNextGuidHob() for matching GUID in HOB list** |  |
| Calculates | **MMIO address for PCIe configuration access** |  |
| Based | **on MCFG table base address** |  |
| Enumerates | **next PCI function (multi-function device support)** |  |
| Checks | **vendor ID != 0xFFFF to detect device presence** |  |
| NETWORK | **NIC BYPASS (HR650X platform specific)** |  |
| Supports | **multiple Riser configurations:** |  |
| Root | **ports: RP 0x1A, 0x2A, 0x3A, 0x3C, 0x1C, 0x2C** |  |
| Skips | **PXE driver binding on NICs behind specified slots** |  |
| Validates | **network device before PXE driver binding** |  |
| Skips | **NICs with >4 ports** |  |

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*Generated by HR650X BIOS Decompilation Project*