# PlatformReset

## Function Table

| Address | Name | Description |
|---------|------|-------------|
|  | **sub_10D0** |  |
|  | **sub_10E0** |  |
|  | **sub_10F0** |  |
|  | **sub_1100** |  |
|  | **sub_1110** |  |
|  | **ModuleEntryPoint** |  |
|  | **PlatformResetDriverEntryPoint** |  |
|  | **PlatformResetUnload** |  |
|  | **PlatformResetEntryPoint** |  |
|  | **PlatformResetSystem** |  |
|  | **nullsub_1** |  |
|  | **sub_1A30** |  |
|  | **sub_1AAC** |  |
|  | **sub_1B34** |  |
|  | **sub_1BF4** |  |
|  | **sub_1C00** |  |
|  | **sub_1CEC** |  |
|  | **sub_1D70** |  |
|  | **sub_1D78** |  |
|  | **sub_1D9C** |  |
|  | **sub_1F68** |  |
|  | **sub_2058** |  |
| Module | **global variables** |  |
| EFI_HANDLE | **ImageHandle      = NULL;    // 0x40C8** |  |
| 0x40B8 | **EFI_BOOT_SERVICES       *gBS             = NULL;   // 0x40C0** |  |
| 0x40D0 | **STATIC EFI_BOOT_SERVICES *mBS             = NULL;   // 0x40F0** |  |
| 0x40D8 | **STATIC EFI_DS            *gDS             = NULL;  // 0x4100** |  |
| 0x40E0 | **STATIC EFI_EVENT          mEfiExitBootServiceEvent = NULL; // 0x40E8** |  |
| 0x4108 | **STATIC VOID              *mHobList        = NULL;  // 0x4110** |  |
| 0x4140 | **STATIC EFI_EVENT          mEfiEventReadyToBoot = NULL; // 0x4148** |  |
| 0x4150 | **STATIC EFI_RUNTIME_SERVICES *mRuntimeServices = NULL; // 0x4160** |  |
| 0x4168 | **STATIC EFI_RESET_SYSTEM   mOriginalResetSystem = NULL; // 0x4170** |  |
| 0x4120 | **STATIC UINTN              mPciExpressMmBaseCount = 0; // 0x4128** |  |
| 0x4138 | **STATIC VOID              *mPciExpressMmBaseRegBase = NULL; // 0x4130** |  |
| 0x4148 | **STATIC BOOLEAN            mRuntimeVirtualAddrMapDone = FALSE; // 0x4118** |  |
| 0x4119 | **//** |  |
| VOID | ***** |  |
| VOID | **sub_10D0 (VOID)** |  |
| UINT64 | **sub_10E0 (VOID)** |  |
| VOID | **sub_10F0 (VOID)** |  |
| VOID | **sub_1100 (VOID)** |  |
| UINTN | **sub_1110 (VOID)** |  |
| ModuleEntryPoint | **- UEFI DXE driver entry point** |  |
| EFI_STATUS | **EFIAPI** |  |
| PlatformResetDriverEntryPoint | **- Initialize driver globals** |  |
| install | **BS protocol notification events, configure** |  |
| PCI | **Express MMIO access and runtime services.** |  |
| r10 | **__int64 v4; // rax** |  |
| rbx | **__int64 v6; // rax** |  |
| r10 | **__int64 v8; // rax** |  |
| rax | **__int64 v10; // rbx** |  |
| rax | **__int64 v12; // rax** |  |
| rbx | **__int64 v14; // rax** |  |
| rax | **__int16 v16; // bx** |  |
| bl | **__int64 v18; // rdi** |  |
| eax | **::ImageHandle = ImageHandle; /*0x1159*/** |  |
| PlatformResetUnload | **- Driver unload handler** |  |
| Unregisters | **runtime PCI Express mappings, frees events.** |  |
| __int64 | **PlatformResetUnload()** |  |
| rax | **__int64 v1; // rbx** |  |
| rax | **__int64 v3; // rax** |  |
| rax | **__int64 v5; // rbx** |  |
| PlatformResetEntryPoint | **- Main entry point for PlatformReset driver.** |  |
| Installs | **the EFI Reset Architecture Protocol and registers** |  |
| the | **PlatformResetSystem() as the runtime ResetSystem handler.** |  |
| EFI_STATUS | **PlatformResetEntryPoint (** |  |
| rax | **__int64 v7; // [rsp+40h] [rbp+8h] BYREF** |  |
| PlatformResetSystem | **- Runtime ResetSystem service handler.** |  |
| Handles | **cold reset (0), warm reset (1), shutdown (3)** |  |
| and | **platform-specific reset (4, 5).** |  |
| Calls | **through PCH SMBus controller or via PCH reset register.** |  |
| rdi | **int n3; // ecx** |  |
| nullsub_1 | **- Null notification function** |  |
| VOID | **nullsub_1 (VOID)** |  |
| sub_1A30 | **- Save the original ResetSystem pointer to mOriginalResetSystem** |  |
| __int64 | **sub_1A30()** |  |
| sub_1A48 | **- ZeroMem with validation (BaseMemoryLib wrapper)** |  |
| __int64 | **__fastcall sub_1A48(__int64 a1, unsigned __int64 a2)** |  |
| sub_1AAC | **- Get the Debug Output protocol for ASSERT/DEBUG output** |  |
| __int64 | **sub_1AAC()** |  |
| rax | **unsigned __int64 n0x10; // rbx** |  |
| rax | **__int64 v3; // rcx** |  |
| sub_1B34 | **- Debug print wrapper (supports NMI lock via CMOS 0x4B)** |  |
| __int64 | **sub_1B34(__int64 a1, const char *a2, ...)** |  |
| rax | **__int64 v4; // r8** |  |
| r9 | **unsigned __int8 v6; // al** |  |
| al | **int n113; // edx** |  |
| sub_1BB4 | **- Debug assert (via Debug Output protocol)** |  |
| __int64 | **__fastcall sub_1BB4(__int64 a1, __int64 a2, __int64 a3)** |  |
| rax | **result = sub_1AAC(); /*0x1bcc*/** |  |
| sub_1BF4 | **- BS event notification: clear gBS pointer** |  |
| VOID | **sub_1BF4 (VOID)** |  |
| sub_1C00 | **- ExitBootServices notification handler** |  |
| VOID | **sub_1C00 (VOID)** |  |
| sub_1C28 | **- Get system configuration table by GUID (UefiLib wrapper)** |  |
| unsigned | **__int64 __fastcall sub_1C28(__int64 a1, _QWORD *a2)** |  |
| r14 | **if ( !a1 ) /*0x1c4a*/** |  |
| sub_1CEC | **- Get HOB list pointer (HobLib wrapper)** |  |
| __int64 | **sub_1CEC()** |  |
| rax | **signed __int64 v1; // rax** |  |
| sub_1D70 | **- SetVirtualAddressMap notification: mark VA map done** |  |
| VOID | **sub_1D70 (VOID)** |  |
| sub_1D78 | **- Runtime event: convert RT pointers for virtual address mode** |  |
| VOID | **sub_1D78 (VOID)** |  |
| sub_1D9C | **- Runtime PCI Express address map cleanup** |  |
| __int64 | **sub_1D9C()** |  |
| rax | **unsigned __int64 v1; // rbx** |  |
| rdi | **result = qword_4120; /*0x1da6*/** |  |
| sub_1E0C | **- Get PCI Express MMIO config space address** |  |
| Resolves | **a PCI Express address to its MMIO base + offset.** |  |
| __int64 | **__fastcall sub_1E0C(__int64 n1024064)** |  |
| rbx | **unsigned __int64 v3; // rax** |  |
| rcx | **if ( (n1024064 & 0xFFFFFFFFF0000000uLL) != 0 ) /*0x1e1c*/** |  |
| sub_1ED0 | **- Compare two GUIDs for equality (ReadUnaligned64 wrapper)** |  |
| bool | **__fastcall sub_1ED0(__int64 a1, __int64 a2)** |  |
| rdi | **__int64 v7; // rax** |  |
| sub_1F38 | **- Read unaligned 64-bit value (BaseLib wrapper)** |  |
| __int64 | **__fastcall sub_1F38(__int64 a1)** |  |
| sub_1F68 | **- Get the PCD protocol pointer** |  |
| __int64 | **sub_1F68()** |  |
| rax | **__int64 v1; // rax** |  |
| sub_1FF4 | **- Write 16-bit I/O port (IoLib wrapper)** |  |
| __int64 | **__fastcall sub_1FF4(_WORD *a1)** |  |
| sub_2028 | **- Read 32-bit I/O port (IoLib wrapper)** |  |
| unsigned | **__int32 __fastcall sub_2028(unsigned __int16 n1288)** |  |
| sub_2058 | **- Free pool memory (MemoryAllocationLib wrapper)** |  |
| __int64 | **sub_2058()** |  |
| rax | **result = (*(__int64 (__fastcall **)(__int64))(qword_40C0 + 72))(qword_4120); /*0x206a*/** |  |

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*Generated by HR650X BIOS Decompilation Project*