# SiInitPreMem

## Function Table

| Address | Name | Description |
|---------|------|-------------|
|  | **PchResetInitCallback** |  |
|  | **PchResetCallback2** |  |
|  | **SetupTraceHubFwBar** |  |
|  | **IsPchSkuSupported** |  |
|  | **IsDwrDetected** |  |
|  | **GetPerformanceLogBuffer** |  |
|  | **RecordPerformanceEntry** |  |
|  | **DebugPrint** |  |
|  | **PpiInstall** |  |
|  | **StartPerformanceMeasurement** |  |
|  | **EndPerformanceMeasurement** |  |
|  | **SiInitPreMemEntryPoint** |  |
|  | **SiInitPrePolicy** |  |
|  | **PrintPchInfo** |  |
|  | **PchWdtInit** |  |
|  | **PchWdtIsUnexpectedReset** |  |
|  | **InstallPchResetPpi** |  |
|  | **InstallPchSpiPpi** |  |
|  | **PchInitPreMem** |  |
|  | **PchAcpiBaseSet** |  |
|  | **PchPwrmBaseGet** |  |
|  | **PchPwrmBaseSet** |  |
|  | **PchTcoBaseSet** |  |
|  | **PchFabricErrorCheck** |  |
|  | **PchEarlyDisabledDeviceHandling** |  |
|  | **GpioInitEarly** |  |
|  | **MmioRead16** |  |
|  | **MmioWrite16** |  |
|  | **PchGetMmPciAddress** |  |
|  | **PchPciRead16** |  |
|  | **PchPciWrite32** |  |
|  | **PchPcrRead32** |  |
|  | **PchPcrWrite32** |  |
|  | **SpiProtocolInit** |  |
|  | **PchInfoGetPchSeriesStr** |  |
|  | **PchInfoGetPchSteppingStr** |  |
|  | **PchInfoGetPchSkuStr** |  |
| Bit | **7 (0x80) indicates SiInitPrePolicy has already been called.** |  |
| volatile | **UINT8  *mSiInitPolicyDoneFlag = (UINT8 *)0xFA044;** |  |
| Perf | **log entry type: the entry point records 0x50E0 as the event** |  |
| type | **(20704 decimal) for the SiInitPrePolicy performance measurement.** |  |
| Module | **global PEI services pointer (maintained across calls)** |  |
| STATIC | **EFI_PEI_SERVICES **mPeiServices = NULL;** |  |
| Forward | **declarations of internal sub-functions** |  |
| PEI | **Services helper: sub_FFD8AD54 / GetPeiServicesPtr** |  |
| Retrieves | **the PEI Services PPI pointer. The implementation reads from** |  |
| the | **IDT-based PEI Services Table Pointer.** |  |
| EFI_PEI_SERVICES | ****** |  |
| Debug | **Output: sub_FFD7F97E / GetDebugInterface** |  |
| Locates | **the ReportStatusCode PPI (GUID: 36232936-0E76-31C8-...)** |  |
| and | **caches it for use by DebugPrint.** |  |
| STATIC | **REPORT_STATUS_CODE_PPI *** |  |
| Debug | **Print: sub_FFD7F9AF** |  |
| Conditional | **debug print via ReportStatusCode PPI.** |  |
| Only | **emits if the requested error level matches the current debug mask.** |  |
| Called | **with:** |  |
| EFI_D_INFO | **(0x40 = 64)   for normal trace messages** |  |
| EFI_D_ERROR | **(0x80000000)  for error/assert messages** |  |
| VOID | **EFIAPI** |  |
| Check | **if the current debug level has this ErrorLevel enabled.** |  |
| The | **debug mask is read from a global variable.** |  |
| DebugMask | **= GetDebugMask ();** |  |
| PPI | **Install: sub_FFD7F948** |  |
| Thin | **wrapper: PeiServices->InstallPpi(PpiList)** |  |
| Performance | **Log: sub_FFD7FBC7 / sub_FFD7FC48** |  |
| Records | **a TSC-based performance entry. Uses a buffer tracked via** |  |
| GetPerformanceLogBuffer | **that returns a log array.** |  |
| STATIC | **VOID** |  |
| Retrieves | **the HOB-based performance log buffer. If no HOB exists** |  |
| Module | **Entry Point: _ModuleEntryPoint (0xffd7f7a1)** |  |
| Phase | **0: One-time initialization guard** |  |
| Check | **bit 7 of the flag byte at mSiInitPolicyDoneFlag (0xFA044).** |  |
| If | **not set, mark as done. This is an anti-double-call protection.** |  |
| if | **((*mSiInitPolicyDoneFlag & BIT7) == 0) {** |  |
| Phase | **1: SiInitPrePolicy - Early silicon policy init (TraceHub)** |  |
| DebugPrint | **(EFI_D_INFO, "SiInitPrePolicy() Start\n");** |  |
| Start | **performance measurement** |  |
| Event | **type = 20704 (0x50E0)** |  |
| StartTsc | **= AsmReadTsc ();** |  |
| Phase | **2a: PchInitPrePolicy - PCH identification** |  |
| PrintPchInfo | **();** |  |
| Phase | **2b: PchInitPrePolicy - WDT, Reset, SPI, GPIO** |  |
| Phase | **3: Notify that SiInitPrePolicy is complete** |  |
| PeiServices | **= GetPeiServicesPtr ();** |  |
| Initializes | **Intel TraceHub (chipset trace/debug hub) MMIO BARs.** |  |
| The | **TraceHub device is at PCI B:D:F 0:20:7 (D20:F7) on the PCH.** |  |
| Get | **PCH power management base address** |  |
| PchPwrmBaseGet | **(&PchPwrmBase);** |  |
| Get | **TraceHub device via PCH MMIO config (D20:F7 = B:D:F 0:20:7)** |  |
| TraceHub | **= (TRACEHUB_DEVICE *)(UINTN)PchGetMmPciAddress (0, 20, 7);** |  |
| Check | **TraceHub presence (VID/DID = 0xFFFF means not present)** |  |
| if | **(MmioRead16 (&TraceHub->VendorId) == 0xFFFF) {** |  |
| Check | **if TraceHub was already initialized (MSE bit)** |  |
| if | **((TraceHub->Command & BIT1) != 0) {** |  |
| DebugPrint | **(EFI_D_INFO, "TraceHubInitialize() - Setting MTB_BAR\n");** |  |
| MSE | **(bit 1) is the minimum - enables MMIO for MTB only** |  |
| Enable | **MSE only initially** |  |
| Check | **SCRPD0.24 to decide if SW/FW BARs should be programmed** |  |
| ScrPd0 | **= *((volatile UINT32 *)TRACE_HUB_SCRPD0_REG);** |  |
| Program | **SW trace buffer frequency and BAR** |  |
| Temporarily | **disable to program BARs** |  |
| Program | **FW_BAR (firmware trace buffer - at offset 0x20)** |  |
| DebugPrint | **(EFI_D_INFO, "TraceHubInitialize() - Setting FW_BAR\n");** |  |
| Enable | **both MSE and BME for full TraceHub operation** |  |
| DebugPrint | **(EFI_D_INFO, "TraceHubInitialize() - Enabling MSE and BME\n");** |  |
| MSE | **+ BME** |  |
| STT | **(Self-Test Trace) disconnected - disable TraceHub** |  |
| Programs | **the TraceHub FW_BAR at PCI config space offset 0x20.** |  |
| This | **is mapped to 0xFE0C0000 with an 8KB window.** |  |
| Check | **DMIC.SRL (DMIC is locked), read from PCR** |  |
| DmicValue | **= PchPcrRead32 (PID_PSF1, 4);** |  |
| Verify | **LPC device is present** |  |
| LpcDevice | **= (UINT32 *)(UINTN)PchGetMmPciAddress (0, 31, 0);** |  |
| Program | **FW_BAR at PCI config offset 0x20 (expansion ROM BAR)** |  |
| with | **value 0xFE0C0000 (8KB).** |  |
| Reads | **PCH device information and logs it via DebugPrint.** |  |
| Get | **PCH series (returns: 1 = LBG, 2 = SPX)** |  |
| Series | **= PchGetSteppingInfo ();** |  |
| Log | **series string** |  |
| BufSize | **= sizeof (SeriesStr);** |  |
| Log | **stepping string** |  |
| BufSize | **= sizeof (SteppingStr);** |  |
| Log | **SKU string** |  |
| BufSize | **= sizeof (SkuStr);** |  |
| 1 | **= PchLbg (Lewisburg / PCH-H): IDs A1C0-A1CF, A243, A240-A24F** |  |
| 2 | **= PchSpx (Sphinx  / PCH-LP): IDs 9D40-9D43, 9D46, 9D48** |  |
| Read | **LPC Device ID from D31:F0 offset +2** |  |
| LpcDeviceId | **= MmioRead16 (** |  |
| Check | **Lewisburg (LBG) range** |  |
| if | **((LpcDeviceId >= V_LBG_DEVICE_ID_MIN && LpcDeviceId <= V_LBG_DEVICE_ID_MAX) ||** |  |
| Check | **Sphinx (SPX) range** |  |
| else | **if (LpcDeviceId == 0x9D40 || LpcDeviceId == 0x9D41 ||** |  |
| Reads | **WDT status from PCH and configures WDT control bits.** |  |
| Check | **WDT status (BIT14)** |  |
| if | **((WdtReadback & BIT14) != 0) {** |  |
| Get | **HOB list from PEI services** |  |
| Determine | **new WDT value based on expiration and unexpected reset** |  |
| if | **((WdtReadback & BIT24) != 0) {** |  |
| Write | **updated WDT value** |  |
| PchPciWrite32 | **(WdtBase, WdtNewValue);** |  |
| Install | **WDT PPIs** |  |
| Status | **= (*PeiServices)->InstallPpi (PeiServices, &gPchWdtPpiGuid);** |  |
| Checks | **whether the WDT unexpected reset flag is set.** |  |
| Installs | **two reset-related PPIs:** |  |
| Allocate | **and install PCH Reset PPI** |  |
| ResetInitPpi | **= (PCH_RESET_PPI *)AllocatePages (EFI_SIZE_TO_PAGES (sizeof (PCH_RESET_PPI)));** |  |
| Install | **second Reset PPI** |  |
| ResetPpi | **= (PCH_RESET_INIT_PPI *)AllocatePages (EFI_SIZE_TO_PAGES (sizeof (PCH_RESET_INIT_PPI)));** |  |
| Program | **SPI BAR0 at D31:F5, offset 0x10 (BAR0)** |  |
| SpiConfig | **= (UINT32 *)(UINTN)PchGetMmPciAddress (0, 31, 5);** |  |
| Enable | **MSE** |  |
| Allocate | **and initialize SPI instance** |  |
| SpiInstance | **= (PCH_SPI_INSTANCE *)AllocatePages (** |  |
| Install | **PPI descriptor** |  |
| Step | **1: Validate PCH SKU (must have LPC device)** |  |
| if | **(!IsPchSkuSupported ()) {** |  |
| Step | **2: Ensure SBREG is programmed (D31:F0, register 0x10/0x14)** |  |
| Step | **3: Program PCH cycle decoding bases** |  |
| PchAcpiBaseSet | **(R_PCH_ACPI_PM_BASE);** |  |
| Step | **4: Validate PCH PWRM base is non-zero** |  |
| DebugPrint | **(EFI_D_INFO, "PCH PWRM Base needs to be programmed before here\n");** |  |
| Step | **5: Check DWR condition** |  |
| DwrDetected | **= IsDwrDetected ();** |  |
| Step | **6: Fabric error check and early device handling** |  |
| Step | **7: Install PCH Init PreMem PPI** |  |
| Status | **= PpiInstall ((EFI_PEI_PPI_DESCRIPTOR *)(UINTN)0xFFD980CC);** |  |
| Validate | **address** |  |
| if | **(AcpiBase == 0 || AcpiBase < 0x100) {** |  |
| Check | **DMIC.SRL (DMIC locked via PCR read)** |  |
| Program | **ACPI base at D31:F2 offset 0x44** |  |
| offset | **0x44** |  |
| clear | **enable bit** |  |
| Verify | **LPC device is present (D31:F0)** |  |
| Read | **PWRM base from D31:F2 offset 0x48** |  |
| PchLpcBridge | **= (UINT32 *)(UINTN)PchGetMmPciAddress (0, 31, 2);** |  |
| Check | **DMIC.SRL lock** |  |
| Access | **D31:F2 for PWRM base config** |  |
| Configure | **PWRM base at offset 0x48** |  |
| PWRM | **base address** |  |
| Check | **DMIC.SRL** |  |
| Access | **D31:F4 for TCO registers** |  |
| PmDevice | **= (UINT32 *)(UINTN)PchGetMmPciAddress (0, 31, 4);** |  |
| Check | **if TCO is already locked** |  |
| if | **(((UINT8 *)PmDevice)[0x54] & 1) {** |  |
| Program | **TCO base at offset 0x54/0x55** |  |
| Iterates | **through a table at unk_FFD980CC defining PSF** |  |
| If | **errors found, creates a HOB with error status.** |  |
| DebugPrint | **(EFI_D_INFO, "PchEarlyDisabledDeviceHandling() - End\n");** |  |
| Configure | **13 groups of 2 GPIO pads each (groups 0x100 through 0x10C)** |  |
| for | **(GpioPad = 256; GpioPad < 269; GpioPad++) {** |  |
| Helper | **functions** |  |
| Check | **DWR (Debug Warranty Reset) condition.** |  |
| Returns | **TRUE if a DWR condition is detected.** |  |
| return | **FALSE;** |  |
| MMIO | **helpers** |  |
| Wait | **for completion** |  |
| while | **((*(volatile UINT32 *)(UINTN)(SbRegBase + 0) & BIT31) != 0) {** |  |

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*Generated by HR650X BIOS Decompilation Project*