# UncoreInitPeim — Purley Platform Uncore/Memory Controller Initialization PEIM

- Module index: 0424
- Port: 13951
- Total functions: 2560
- Named: 2453 (95.8%)
- Unnamed: 107 (sub_*, AutoGen*, still unnamed)

## Module Classification

This is the **Intel Purley/Skylake-SP Uncore and Memory Controller initialization PEIM** executing during the PEI phase of UEFI boot. It initializes the CPU's uncore subsystem including the memory controller (MC), IIO (Integrated I/O), KTI (Keizer Technology Interconnect — Intel's UPI), PCIe root complexes, DDR4/DDRT memory training, and SMBus mailbox communication with the PCODE microcontroller.

**Key functional domains:**
- **Memory Init (MRC)**: DDR4 training, timing calibration, DQ/DQS training, write leveling, margin testing, rank configuration, SPD parsing, NVDIMM init
- **IIO/PCIe**: PCIe bus early init, address routing, link training, hot reset
- **KTI (UPI)**: Socket interconnect initialization, frequency selection, coherence setup, RAS configuration
- **PCODE Mailbox**: SMBus-based communication with the power management microcontroller for voltage/freq settings
- **Platform Config**: SKU detection, socket count, platform data initialization, manufacturing test hooks
- **SMBus**: SMBus controller initialization, SPD read, PCODE commands

## Key Functions

### Entry & Main Flow
- `_ModuleEntryPoint` (0xffc1e919): PEI module entry point
- `UncoreInitEntry` (0xffc28e01): Entry dispatcher
- `UncoreInitMain` (0xffc29939): Main initialization orchestrator (4a6 bytes)
- `ProcMemInitMain` (0xffc52c8e): Memory initialization main (1493 bytes)

### DDR4 Memory Training
- `Ddr4TrainingMain` (0xffc6bda9): Main DDR4 training routine
- `MemTestScramTest` (0xffc212cf): Memory test scramble pattern
- `DataCmdCtlTrain` (0xffc30f68): Command/control bus training
- `ReadDqDqsCleanup` (0xffc32d95): DQ/DQS read path cleanup
- `DdrTimingTraining` (0xffc6f77b): DDR timing training
- `DimmSpdTimingInit` (0xffc79494): SPD-based timing initialization
- `DimmConfigPerSocket` (0xffc2a729): Per-socket DIMM configuration
- `DimmCommTest` (0xffc3e8f5): DIMM communication test
- `Ddr4DdrtMixedConfig` (0xffc6f323): DDR4/DRT mixed config handling
- `Ddr4SkuCheck` (0xffc7fdf5): DDR4 SKU validation
- `WriteLevelingPushPull` (0xffc7f2f6): Write leveling calibration
- `MemAdvTestFailureCheck` (0xffc270b2): Advanced test failure analysis
- `IOTrainingCtlCmdCkeClk` (0xffc7bcff): IO training CMD/CKE/CLK control
- `Ddr4RcdInit` (0xffc7d4db): RCD (Registering Clock Driver) init
- `NgnDimmThermalThrottle` (0xffc6cf67): Next-gen DIMM thermal throttling
- `NgnDimmPmonInit` (0xffc6ebba): Power monitoring init
- `NgnDimmCmdControl` (0xffc6edc3): Command control for NVDIMM
- `NgnDimmThermalUpdate` (0xffc6ef73): Thermal update for NVDIMM
- `DimmPartitionDdrt` (0xffc8b828): DDRT partition configuration
- `DimmInterleaveConfig` (0xffc83e2f): DIMM interleave configuration
- `DimmReadLinkMcaData` (0xffc95ccb): Read link MCA (Machine Check) data
- `DimmSpareRankConfig` (0xffc97a43): Spare rank configuration
- `DimmSetSpareMode` (0xffc97e26): Spare mode setting
- `DimmExecuteSmartPpr` (0xffc9c097): Smart Post-Package Repair execution
- `DdrtConfigValidation` (0xffc77b62): DDRT config validation
- `DdrCheckVmseErrLatency` (0xffc7765a): VMSE error latency check

### Memory Controller
- `MemInitWrapper` (0xffc301d1): Memory initialization wrapper
- `ProcMemInitSetup` (0xffc329e1): Memory init setup
- `ProcMemInitCommon` (0xffc40cab): Common memory init routine
- `MemInitiateSktUpdate` (0xffc43fa2): Per-socket memory update
- `MemInitChipMain` (0xffc814a2): Chip-specific memory init
- `MemCpgcMain` (0xffc7e5a9): CPGC (Channel Power Gating Calibration) main
- `CpgcChannelInit` (0xffc5e7f8): Per-channel CPGC init
- `CpgcSktInit` (0xffc6410c): Per-socket CPGC init
- `MrcHooksChipServices` (0xffc4ee0a): MRC hook chip services
- `MrcMarginGroupTrain` (0xffc4e1c5): Margin group training
- `MrcPpibControl` (0xffc28f7b): PPIB (Parallel Peripheral Interface Bus) control
- `PostMrcInitConfig` (0xffca6b89): Post-MRC configuration
- `MemCmdControlSetup` (0xffc8dcee): Memory command control setup

### IIO and PCIe
- `PcieAddressInit` (0xffc1f9ae): PCIe address initialization
- `PcieAddressEarlyInit` (0xffc65886): Early PCIe address init
- `PcieEarlyInit` (0xffc28eaa): Early PCIe initialization
- `PciAccessInit` (0xffc576da): PCI access initialization
- `PciCfgRead` (0xffc2abce): PCI config read wrapper
- `PciCfgWrite` (0xffc2ad08): PCI config write wrapper
- `IioEarlyLinkInit` (0xffc2dfad): IIO early link initialization
- `IioResetCheck` (0xffca6a76): IIO reset state check

### KTI (UPI) Interconnect
- `KtiInitMain` (0xffc2b95c): KTI initialization main
- `KtiSelectFreq` (0xffc680ee): KTI frequency selection
- `KtiLibSocketCheck` (0xffc3628d): Socket presence check
- `KtiLibAssertCheck` (0xffc36b45): KTI assert/error check
- `KtiMainSocketCheck` (0xffc43a80): Main socket validation
- `KtiMainCheckMaxSocket` (0xffc474e9): Max socket count check
- `KtiMainCheckTotalCpu` (0xffc47a8a): Total CPU count check
- `KtiSetRasConfig` (0xffc97461): RAS configuration for KTI
- `KtiEvAutoRecipeMain` (0xffc9613a): Auto recipe training
- `KtiLinksMain` (0xffc9908e): KTI link management
- `KtiCohMain` (0xffc9e6a6): KTI coherence setup
- `KtiDiscoveryFunc0606` (0xffca0606): KTI discovery / enumeration
- `KtiDebugAssert` (0xffc391bb): KTI debug assert
- `KtiDebugPrint` (0xffc391e2): KTI debug print

### PCODE Mailbox (SMBus)
- `MailBoxPcodeComm` (0xffc42cd1): PCODE mailbox communication (9c2 bytes)
- `MailBoxPcodeCmd` (0xffc5de32): PCODE mailbox command
- `MailBoxSendRecv` (0xffc5a7f5): Mailbox send/receive (b09 bytes)
- `SmbusInit` (0xffc50d60): SMBus controller init
- `SmbusReadBlock` (0xffc5e13a): SMBus block read

### CPU and Platform Init
- `CpuCfgEarlySetup` (0xffc2afce): Early CPU configuration
- `CpuFeatureEarlyConfig` (0xffc2beae): Early CPU feature config
- `CpuIssActiveCoreCheck` (0xffc2c9da): ISS active core check
- `CpuIoRead` (0xffc2af4f): CPU IO read
- `CpuIoCfgWrite` (0xffc2af92): CPU IO config write
- `CpuInitB0CA` (0xffc3b0ca): CPU initialization
- `GetSocketNumber` (0xffc2aec8): Socket number query
- `SkuInitPrepare` (0xffc28f46): SKU init preparation
- `SkuingDataInit` (0xffca7653): SKU data initialization
- `NetInit` (0xffc63295): MRC network init
- `IpInit` (0xffc69649): MRC IP init
- `CheckAndDispatch` (0xffca7738): Event check and dispatch
- `Assert` / `Assert_0` / `Assert_1` (0xffc67e26, 0xffc69a2a, 0xffc6accd): Assertion handlers
- `SetMem` (0xffca7a86): Memory set helper
- `CheckPpiAvailable` (0xffca7673): PEIM-to-PEIM Interface (PPI) availability check

### Platform Hooks
- `InitializeDefaultData` (0xffc2928b): Default data init
- `InitializePlatformData` (0xffc297a5): Platform data init
- `PlatformDataEarlyInit` (0xffca7838): Early platform data
- `PlatformPostInit` (0xffca76f8): Platform post-init
- `PlatformFinalInit` (0xffca79c5): Platform final init
- `PlatformDataLateInit` (0xffca7aeb): Late platform data init
- `CollectPrevBootFatalErrors` (0xffc29ddf): Previous boot error collection
- `CheckResetRequest` (0xffc2b06a): Reset request check
- `PipeInitMain` / `PipeExitMain` (0xffc2b24b / 0xffc2b18c): Pipe init/exit
- `MiscConfigCheck` (0xffc58d42): Miscellaneous config check
- `MiscIoCheck` (0xffc58f0b): Miscellaneous IO check
- `RcAssertPrint` (0xffca7715): RC assert print
- `ProcMemInitCheck` (0xffc2a26a): Memory init check
- `UsraRegisterFilter` (0xffc1ec31): USRA register filter (d5e bytes)

## Structures

### PCIE_ADDRESS_TABLE (identified by structure-identifier agent)
PCIe address mapping table used by `PcieAddressInit` and `PcieAddressEarlyInit` for configuring PCIe bus address routing on the Purley platform.

## Platform

This module targets the **Intel Purley platform** (Skylake-SP Xeon Scalable) based on:
- KTI (UPI) interconnect for socket-to-socket communication
- DDR4 memory training with DDRT (DDR-T) mixed config support
- IIO (Integrated I/O) for PCIe root complex management
- PCODE SMBus mailbox interface for power management
- CPGC (Channel Power Gating Calibration) for memory power management
- NVDIMM support (thermal, power monitoring, command control)
- USRA (Uncore System Register Access) for register filtering

## Function List