# SBDXE

## Function Table

| Address | Name | Description |
|---------|------|-------------|
|  | **GetPcdProtocol** |  |
|  | **SbdInstallPcieSegBusTable** |  |
|  | **SbdAssert** |  |
|  | **SbdDebugPrint** |  |
|  | **GetPciExpressBaseAddress** |  |
|  | **GetPchSku** |  |
|  | **GetPchStepping** |  |
|  | **XhciWrite32** |  |
|  | **XhciRead32** |  |
|  | **XhciDisablePort** |  |
|  | **UsbPerPortDisableCallback** |  |
|  | **SaveBootScriptToLockBox** |  |
|  | **SetBootScriptLockBoxAttributes** |  |
|  | **InitBootScriptTable** |  |
|  | **BootScriptReadyToLockNotify** |  |
|  | **BootScriptCloseNotify** |  |
|  | **CloseBootScriptTable** |  |
|  | **BootScriptContextCloseNotify** |  |
|  | **InitializeDxeServices** |  |
|  | **LocateSmmCommunicationProtocol** |  |
|  | **InitializeLibGlobals** |  |
|  | **SBDxeInitialize** |  |
|  | **SBDxeEntryPoint** |  |
|  | **PciExpressRead32** |  |
|  | **PciExpressWrite32** |  |
|  | **IoRead16** |  |
|  | **IoWrite16** |  |
|  | **IoRead32** |  |
|  | **IoWrite32** |  |
|  | **IoRead8** |  |
|  | **IoWrite8** |  |
|  | **MemZero** |  |
| Global | **Data** |  |
| EFI_HANDLE | **gImageHandle       = NULL;** |  |
| HOB | **list pointer (from DXE HOB library)** |  |
| VOID | ***gHobList  = NULL;** |  |
| PciUsra | **(MM PCI base) from DxeMmPciBaseLib** |  |
| VOID | ***gPciUsra  = NULL;** |  |
| PciExpress | **Base Address (from PCD)** |  |
| UINT64 | **gPciExpressBaseAddr = 0;** |  |
| PCH | **stepping / SKU global state** |  |
| UINT32 | **gPchStepping = 3;    ///< Initial state; determined at first call** |  |
| Boot | **Script / S3 state** |  |
| UINT64 | **gBootScriptTable     = 0;** |  |
| XHCI | **USB port disable state: set to TRUE after first callback** |  |
| BOOLEAN | **gXhciPortDisableDone = FALSE;** |  |
| PCD | **protocol, SMM Communication protocol** |  |
| VOID | ***gPcdProtocol         = NULL;** |  |
| PciUsra | **via SMM PCI base protocol** |  |
| STATIC | **VOID  *mPciUsra = NULL;** |  |
| GUID | **Definitions** |  |
| EFI_GUID | **gPchRcConfigGuid            = { 0x6350F689, 0x6EF9, 0x4B9A, { 0x87, 0xA0, 0xBB, 0xF6, 0x4D, 0x35, 0x08, 0xED }};** |  |
| GUID | **for PiSmmCommunicationRegionTable (for SMM LockBox)** |  |
| EFI_GUID | **gSmmCommRegionGuid          = { 0x8E7BE0F9, 0x3D41, 0x42D9, { 0x9F, 0xFF, 0xAC, 0xC0, 0x88, 0xC2, 0xC8, 0x32 }};** |  |
| Function | **Prototypes (local)** |  |
| STATIC | **EFI_STATUS** |  |
| Internal | **helper: ASSERT macro with message** |  |
| PCH | **SKU Detection** |  |
| Read | **LPC/eSPI device ID from PCI config space (Bus 0, Dev 31, Func 0, offset 2)** |  |
| LpcDevId | **= IoRead16 (PCI_EXPRESS_LIB_ADDRESS (0, 31, 0, 0x02));** |  |
| Check | **if device ID falls in the PCH-H range** |  |
| if | **(((LpcDevId + 24128) & 0xFF70) == 0) {** |  |
| This | **is PCH-H (SKU 1)** |  |
| Sku | **= 1;** |  |
| This | **is PCH-LP (SKU 2)** |  |
| Sku | **= 2;** |  |
| PCH | **Stepping Detection** |  |
| Read | **the PCH RID (Revision ID) from PCI config** |  |
| Get | **the base address for PCH info from the PchInfoLib** |  |
| PchInfoBase | **= PciExpressRead32 (** |  |
| Read | **the LPC device ID for stepping decode** |  |
| Decode | **stepping based on Device ID + Rev ID** |  |
| if | **(((LpcDeviceId + 24128) & 0xFF70) == 0) {** |  |
| switch | **(RevId) {** |  |
| A0 | **case 0x10:** |  |
| A1 | **case 0x20:** |  |
| A2 | **case 0x30:** |  |
| B0 | **case 0x31:** |  |
| B1 | **default:** |  |
| if | **((UINT16)(LpcDeviceId + 25280) <= 8) {** |  |
| C1 | **/ LP D0** |  |
| C2 | **/ LP D1** |  |
| C3 | **/ LP D2** |  |
| C4 | **/ LP D3** |  |
| If | **none of the above, check for D/E stepping** |  |
| if | **(((LpcDeviceId + 24128) & 0xFF70) != 0) {** |  |
| Check | **the RTC CMOS register for stepping hints** |  |
| D0 | **} else if (RevId == 2) {** |  |
| D1 | **} else if (RevId == 3) {** |  |
| D2 | **} else if (RevId == 4) {** |  |
| D3 | **} else if (RevId == 5) {** |  |
| E0 | **} else if (RevId == 6) {** |  |
| E1 | **} else {** |  |
| Unknown | **}** |  |
| XHCI | **Per-Port Disable Logic** |  |
| Port | **is already disabled, nothing to do.** |  |
| Issue | **port disable** |  |
| if | **(IsSSPort) {** |  |
| For | **SS ports, set Port Disable + Reset** |  |
| XhciWrite32 | **(XhciBar, PortBase, 0x8000FE00);** |  |
| Wait | **up to 3 seconds (3000 * 1ms)** |  |
| for | **(Timeout = 0; Timeout < 3000; Timeout++) {** |  |
| For | **HS ports, set Port Reset + Port Disable** |  |
| XhciWrite32 | **(XhciBar, PortBase, 0x210);** |  |
| Wait | **up to 200ms (200 * 1ms)** |  |
| for | **(Timeout = 0; Timeout < 200; Timeout++) {** |  |
| Determine | **PCH SKU for port count and register layout** |  |
| Sku | **= GetPchSku ();** |  |
| Read | **PchRcConfiguration variable from runtime services** |  |
| ConfigDataSize | **= sizeof (PortConfig);** |  |
| Read | **XHCI BAR** |  |
| ConfigRequest | **= 0xA0010;  // EFI_PCI_IO_ATTRIBUTE_MEMORY** |  |
| XhciBar | **= PciExpressRead32 (PCI_EXPRESS_LIB_ADDRESS (0, 20, 0, 0x10));** |  |
| Handle | **64-bit BAR if needed** |  |
| if | **((PciExpressRead32 (PCI_EXPRESS_LIB_ADDRESS (0, 20, 0, 0x10)) & 0x06) == 0x04) {** |  |
| Read | **current HS PDO, SS PDO, and SSPE values** |  |
| HsPdo | **= XhciRead32 (XhciBar, XHCI_HSPDO_OFS);** |  |
| Process | **HS (USB 2.0) ports** |  |
| for | **(PortIndex = 0; PortIndex < MaxHsPorts; PortIndex++) {** |  |
| User | **wants port disabled** |  |
| HsPdo | **&= ~DisableMask;** |  |
| User | **wants port enabled** |  |
| HsPdo | **|= DisableMask;** |  |
| Process | **SS (USB 3.0) ports** |  |
| for | **(PortIndex = 0; PortIndex < MaxSsPorts; PortIndex++) {** |  |
| Compute | **SSPE value** |  |
| if | **(PortConfig[1254] != 0) {** |  |
| All | **SS ports explicitly managed** |  |
| if | **(Sku == 2) {** |  |
| Derive | **SSPE from SS PDO** |  |
| SsPe | **= SsPdo;** |  |
| Write | **back the PDO and SSPE registers** |  |
| DEBUG | **((DEBUG_INFO, "Write back Xhci HS PDO value: %x to HS PDO register\n", HsPdo));** |  |
| Now | **physically disable each port that was marked for disable** |  |
| This | **HS port needs to be disabled** |  |
| if | **(PortIndex < 12) {** |  |
| This | **SS port needs to be disabled** |  |
| Boot | **Script Support** |  |
| Prepare | **SMM communication buffer for LockBox save** |  |
| BufferPtr | **= &LocalBuffer[0];** |  |
| Build | **the LockBox communication buffer:** |  |
| CopyMem | **(BufferPtr, &gBootScriptContextGuid, sizeof (EFI_GUID));** |  |
| EFI_SMM_LOCK_BOX_COMMAND_SAVE | ***((UINT64 *)&BufferPtr[24]) = (UINT64)-1;** |  |
| EFI_SMM_LOCK_BOX_SIGNATURE | ***((UINT32 *)&BufferPtr[36]) = 48;    // Header size** |  |
| Build | **LockBox communication buffer for SetAttributes command** |  |
| Header | **version** |  |
| Header | **size** |  |
| LOCK_BOX_ATTRIBUTE_RESTORE_IN_PLACE | **CommSize = 64;** |  |
| S3 | **Boot Script Initialization** |  |
| Allocate | **runtime memory page for the boot script table** |  |
| Status | **= gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, 1, &PcdValue);** |  |
| Store | **the PCD value for the boot script table address** |  |
| PcdSet64S | **(PcdBootScriptTableAddress, PcdValue);** |  |
| Signal | **that the boot script table is ready** |  |
| gBootScriptTable | **= PcdValue;** |  |
| Register | **notification for DxeSmmReadyToLock** |  |
| EfiCreateEventReadyToBoot | **(** |  |
| Close | **event notification** |  |
| Lock | **the boot script table** |  |
| Save | **the current boot script data to LockBox** |  |
| Set | **LockBox attributes** |  |
| SetBootScriptLockBoxAttributes | **();** |  |
| Register | **for subsequent boot script close events** |  |
| if | **(gSmmCommunicationProtocol != NULL) {** |  |
| Register | **close event callbacks for S3 resume paths** |  |
| Additional | **cleanup callbacks** |  |
| Copy | **the new table to the LockBox** |  |
| Restore | **the PCD to the locked value** |  |
| PcdSet64S | **(PcdBootScriptTableAddress, gBootScriptTable);** |  |
| PCIe | **Segment Bus Table Setup** |  |
| Get | **the number of PCIe segments from PCD** |  |
| PcdProtocol | **= GetPcdProtocolPtr ();** |  |
| Allocate | **and initialize the bus table** |  |
| PcieSegBusTable | **= AllocateZeroPool (NumSegments);** |  |
| Call | **the PCH-specific installation routine** |  |
| PCIe | **config base** |  |
| PCI | **Express Base Address Initialization** |  |
| DXE | **Service Table and HOB List Discovery** |  |
| SMM | **Communication Protocol Discovery** |  |
| Library | **Constructor-Style Init** |  |
| Cache | **UEFI core services** |  |
| gImageHandle | **= ImageHandle;** |  |
| Initialize | **DXE services table and HOB list from configuration table** |  |
| Main | **Driver Initialization** |  |
| InitializeLibGlobals | **(ImageHandle, SystemTable);** |  |
| This | **driver uses the simpler callback registration model.** |  |
| Status | **= gBS->LocateProtocol (** |  |
| SMM | **protocol may not be available yet; we try again in callbacks.** |  |
| gPciUsra | **= NULL;** |  |
| Stepping | **= GetPchStepping ();** |  |
| Also | **used to enable write-combining for PCIe MMIO range** |  |
| Enable | **PCIe ECAM (enhanced configuration access mechanism)** |  |
| IoWrite16 | **(PcdGet16 (PcdPciExpressBaseAddress), 0x500);** |  |
| IsPchLp | **= (GetPchSku () == 2);** |  |
| while | **(((TimeoutValue + 357 - IoRead32 (PcdGet16 (PcdAcpiBaseAddress))) & 0x800000) == 0) {** |  |
| if | **(IsPchLp) {** |  |
| Status | **= InitBootScriptTable (&gBootScriptTable);** |  |
| Status | **= gBS->CreateEvent (** |  |
| Module | **Entry Point** |  |
| Invoke | **the main initialization routine** |  |
| Status | **= SBDxeInitialize (ImageHandle, SystemTable);** |  |
| Assertion | **/ Debug Helpers** |  |
| PCI | **Express MMIO Read/Write Helpers (used for chipset access)** |  |
| IO | **Port Helpers** |  |
| Use | **aligned copy for speed when possible.** |  |
| Fall | **back to byte copy for tail bytes.** |  |
| if | **((Src < Dest) && ((UINT8 *)Src + Count - 1 >= (UINT8 *)Dest)) {** |  |
| CopyMemBackwards | **(Dest, Src, Count);** |  |

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*Generated by HR650X BIOS Decompilation Project*