# PchInitDxe

## Function Table

| Address | Name | Description |
|---------|------|-------------|
|  | **PchInitDxeEntry** |  |
|  | **PchInitEntryPoint** |  |
|  | **PchInitGlobalDataInit** |  |
|  | **PchInitS3BootScriptInit** |  |
|  | **PchS3BootScriptDeinit** |  |
|  | **PchInitS3BootScriptSave** |  |
|  | **PchRevealTraceHub** |  |
|  | **PchUplinksInit** |  |
|  | **InitializePchDevice** |  |
|  | **PchUsbPrecondition** |  |
|  | **PchUsbPreconditionTimerCallback** |  |
|  | **ConfigurePmForRstRemapping** |  |
|  | **PchPcieRpEarlyConfig** |  |
|  | **PchConfigureRpfnMapping** |  |
|  | **PchOnEndOfDxe** |  |
|  | **PchOnEndOfDxeWrapper** |  |
|  | **PchOnReadyToBoot** |  |
|  | **PchOnReadyToBootEx** |  |
|  | **PchOnExitBootServices** |  |
|  | **PchOnProtocolNotify** |  |
|  | **PchOnSmmReadyToLockNotify** |  |
|  | **PchOnSmmReadyToBootNotify** |  |
|  | **PchAcpiOnEndOfDxe** |  |
|  | **InstallPchNvsProtocol** |  |
|  | **PchUpdateNvsArea** |  |
|  | **PublishNhltAcpiTable** |  |
|  | **LockDownUnusedRstPcie** |  |
|  | **ConfigureRstPcieStorageRemapping** |  |
|  | **RstPcieStorageRemappingLateConfig** |  |
|  | **DetectPcieStorageDevices** |  |
|  | **PcieEndPointL1ssConfig** |  |
|  | **_ModuleEntryPoint** |  |
|  | **PchOnSmmCommunication** |  |
|  | **PchSteppingCheck** |  |
|  | **PchInfoLibGetPchSku** |  |
|  | **PchInfoLibGetLpcDeviceId** |  |
|  | **PchPcrRead** |  |
|  | **PchPcrWrite** |  |
|  | **PchP2sbRead** |  |
|  | **PchCycleDecodingAcpiBaseIsSet** |  |
|  | **PchCycleDecodingAcpiBaseGet** |  |
|  | **PchCycleDecodingPwrmBaseGet** |  |
|  | **UefiLibCreateReadyToBootEvent** |  |
|  | **UefiLibCreateLegacyBootEvent** |  |
|  | **GetPchPcieRpDevFun** |  |
|  | **GetPchPcieRpNumber** |  |
|  | **MemoryFreePool** |  |
|  | **MemoryStall** |  |
|  | **IoDelayShort** |  |
|  | **IoDelayEnd** |  |
| Global | **Variable Definitions** |  |
| UEFI | **core globals (set by PchInitDxeEntry)** |  |
| PCD | **- PCIe Segment Bus Table** |  |
| max | **PCD size** |  |
| PCH | **Policy HOB (from PEI phase)** |  |
| HOB | **list pointer** |  |
| PCH | **LPC bridge MMIO base** |  |
| USB | **Precondition context** |  |
| USB | **ACPI timer tracking** |  |
| PCH | **NVS Area pointer** |  |
| PCIe | **IO Trap address** |  |
| S3 | **Boot Script globals** |  |
| L1SS | **memory pool allocator** |  |
| L1SS | **configuration table** |  |
| NHLT | **feature enable flags** |  |
| Saved | **ImageHandle copy** |  |
| Private | **Function Prototypes** |  |
| Module | **Entry Point** |  |
| SECTION | **1: Initialization Sequence** |  |
| Get | **DxeServicesTable** |  |
| Get | **PCI USRA protocol** |  |
| Initialize | **HOB list** |  |
| Copy | **PCIe Segment Bus Table from PCD** |  |
| PCH | **debug port sequence (POST code 0x80)** |  |
| enable | **POST** |  |
| delay | **loop** |  |
| restore | **original state** |  |
| Initialize | **S3 boot script system** |  |
| Load | **SATA RSTe Option ROM if configured** |  |
| Load | **Secondary SATA RSTe Option ROM** |  |
| config | **version** |  |
| USB | **Precondition** |  |
| Configure | **Power Management for RST Remapping** |  |
| Early | **PCIe RP configuration (ASPM/L1SS)** |  |
| Configure | **RP Function Number mapping** |  |
| Install | **device config protocol** |  |
| allocation | **failure** |  |
| SECTION | **2: PCH Device Configuration** |  |
| PMC | **base: read PCR, set SLP_S0 and various PM registers** |  |
| enable | **PMC** |  |
| Configure | **P2SB MMIO base and hide** |  |
| For | **each GPIO community, configure PCR pad config registers** |  |
| Configure | **SATA BARs, interrupt, and port enable** |  |
| Get | **RP device/function** |  |
| Read | **config space header** |  |
| Check | **for device present (Vendor ID != 0xFFFF)** |  |
| Program | **ASPM for this RP** |  |
| Program | **L1SS for this RP** |  |
| Configure | **GPIO CLKREQ for this RP** |  |
| not | **RAID mode** |  |
| Get | **SATA controller MMIO base** |  |
| Program | **port power management registers** |  |
| Port | **not used by RST - configure power management** |  |
| Configure | **per-port GPIO CLKREQ** |  |
| Program | **SATA controller power management** |  |
| SECTION | **3: USB Precondition** |  |
| Locate | **XHCI PCI IO protocol** |  |
| Get | **XHCI MMIO base** |  |
| Enable | **XHCI MMIO** |  |
| enable | **bus master** |  |
| Get | **USB2 port count from XHCI capability registers** |  |
| Allocate | **precondition context** |  |
| Build | **port bitmap** |  |
| Set | **timer handler** |  |
| Restore | **XHCI MMIO config** |  |
| Close | **XHCI MMIO window** |  |
| Wait | **for ACPI timer synchronization** |  |
| Timer | **progressed, OK** |  |
| Get | **XHCI MMIO base and program ports** |  |
| Program | **port for warm reset** |  |
| SECTION | **4: Uplink Port Programming** |  |
| Determine | **PCH SKU** |  |
| Found | **x16 Uplink (Device ID = 0x37C0)** |  |
| Program | **Max Payload Size** |  |
| Program | **Max Read Size** |  |
| Program | **downstream ports (function 0-5)** |  |
| No | **secondary uplink needed** |  |
| Find | **x8 Uplink** |  |
| Found | **x8 Uplink (Device ID = 0x37C1)** |  |
| Program | **downstream port at function 2** |  |
| SECTION | **5: ACPI NVS Protocol** |  |
| Allocate | **NVS buffer (0x26D bytes)** |  |
| Set | **signature** |  |
| Install | **protocol** |  |
| Copy | **GPIO group info into NVS buffer** |  |
| Register | **ACPI EndOfDxe processing** |  |
| Set | **GPIO port config** |  |
| Set | **SATA port presence** |  |
| Set | **PCIe segment bus number for NVS** |  |
| Fill | **in PCIe RP BDF per port** |  |
| Set | **PCH SKU and LPC Device ID** |  |
| Get | **P2SB value** |  |
| Set | **TraceHub enable flag** |  |
| Configure | **GPIO pad ownership** |  |
| Set | **per-port GPIO pad native function status** |  |
| Set | **SATA port SSD presence** |  |
| Find | **SATA port with speed 20 / multiplier 2** |  |
| SECTION | **6: ACPI EndOfDxe Processing (NHLT + NVS Patch)** |  |
| Check | **HD Audio presence** |  |
| Update | **NVS area** |  |
| Initialize | **ASL update library** |  |
| Patch | **PCH NVS address into ASL (Name: NPCH, value: NVS base)** |  |
| 0x4843504E | **(INT16 *)&NvsAddr** |  |
| 0x4C43504E | **&NvsSegment** |  |
| SECTION | **7: NHLT ACPI Table Publishing** |  |
| Parse | **feature mask to set global enable flags** |  |
| Locate | **ACPI table protocol** |  |
| Construct | **NHLT endpoints** |  |
| Construct | **NHLT header** |  |
| Install | **ACPI table** |  |
| Locate | **NHLT from existing RSDT/XSDT for NVS update** |  |
| Scan | **XSDT/RSDT for NHLT signature** |  |
| Update | **NVS area with NHLT address/length** |  |
| SECTION | **8: EndOfDxe Processing** |  |
| Lock | **down unused RST PCIe on primary SATA** |  |
| Lock | **down unused RST PCIe on secondary SATA (if present)** |  |
| Get | **PCIe IO Trap address** |  |
| Process | **locks in InitializePchDevice** |  |
| Program | **PCIe IO Trap boot script** |  |
| IO_WRITE | **opcode** |  |
| width | **= UINT16** |  |
| Write | **entry to boot script** |  |
| P2SB | **hide** |  |
| ACPI | **base disable** |  |
| Signal | **OS handoff in NVS area** |  |
| SECTION | **9: Protocol Notify Callback** |  |
| Check | **if PchSmmProtocol is already installed** |  |
| Already | **installed, skip** |  |
| Initialize | **Uplink ports** |  |
| Configure | **xHCI MMIO** |  |
| Check | **PCH stepping for LPC config** |  |
| Reveal | **TraceHub if PMC not configured** |  |
| Check | **xHCI status** |  |
| SECTION | **10: TraceHub Configuration** |  |
| Check | **if TraceHub is disabled in policy** |  |
| Program | **TraceHub FW_LBAR and SW_LBAR** |  |
| FW_LBAR | **high** |  |
| SW_LBAR | **low** |  |
| SECTION | **11: SATA Lockdown** |  |
| Primary | **SATA (Device 23, Function 0)** |  |
| Secondary | **SATA (Device 17, Function 5)** |  |
| SATA | **lockdown** |  |
| SECTION | **12: S3 Boot Script** |  |
| Check | **if boot script is already initialized (via PCD 137)** |  |
| Set | **PCD to store boot script pointer** |  |
| Register | **for SmmReadyToLock notification** |  |
| Save | **boot script table pointer** |  |
| Check | **for SMM base2 protocol** |  |
| Allocate | **SMM boot script buffer** |  |
| Register | **SMM communication handlers** |  |
| SECTION | **13: Protocol Notify (SMM)** |  |
| Handle | **SMM communication for boot script** |  |
| SECTION | **14: Helper Function Stubs** |  |
| Close | **events, free buffers** |  |
| Returns | **PCH stepping mask** |  |
| Each | **PCH PCIe RP occupies 1 device with 1 function** |  |
| Short | **delay for PCH register programming** |  |

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*Generated by HR650X BIOS Decompilation Project*