/** @file
  LegacySredir.h -- Header for LegacySredir

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __LEGACYSREDIR_H__
#define __LEGACYSREDIR_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
ReadUnaligned64(
  VOID
);

EFI_STATUS
EFIAPI
DebugClearMemory(
  VOID
);

EFI_STATUS
EFIAPI
DebugPrint(
  VOID
);

EFI_STATUS
EFIAPI
DebugAssert(
  VOID
);

EFI_STATUS
EFIAPI
HobGuidMatch(
  VOID
);

EFI_STATUS
EFIAPI
IoOrMemWrite(
  VOID
);

EFI_STATUS
EFIAPI
UartInitConfigRegisters(
  VOID
);

EFI_STATUS
EFIAPI
SioUartRegisterSetup(
  VOID
);

EFI_STATUS
EFIAPI
InitPchRcConfiguration(
  VOID
);

EFI_STATUS
EFIAPI
SioSetupRegisterDevice(
  VOID
);

EFI_STATUS
EFIAPI
SmmRuntimeServicesNotify(
  VOID
);

EFI_STATUS
EFIAPI
LegacySerialRedirectionRegister(
  VOID
);

EFI_STATUS
EFIAPI
LegacySerialRedirectionUnregister(
  VOID
);

EFI_STATUS
EFIAPI
SmmReadyToBootCallbackRegister(
  VOID
);

EFI_STATUS
EFIAPI
SmmSwDispatch2Callback(
  VOID
);

EFI_STATUS
EFIAPI
SmmBase2Communicate(
  VOID
);

EFI_STATUS
EFIAPI
LegacySredirDriverEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
Variables(
  VOID
);

EFI_STATUS
EFIAPI
Boot/Runtime Services Table pointers(
  VOID
);

EFI_STATUS
EFIAPI
*gBS;              // 0x2400(
  VOID
);

EFI_STATUS
EFIAPI
EFI_SYSTEM_TABLE       *gST;              // 0x2410(
  VOID
);

EFI_STATUS
EFIAPI
Protocol interface (resolved from protocol GUID at 0x2260)(
  VOID
);

EFI_STATUS
EFIAPI
for Super I/O register access via PCI configuration space.(
  VOID
);

EFI_STATUS
EFIAPI
*gSioProtocol;     // 0x2390(
  VOID
);

EFI_STATUS
EFIAPI
protocols(
  VOID
);

EFI_STATUS
EFIAPI
*gSmmSwDispatch2Protocol;   // 0x2378 - GUID 0x2290(
  VOID
);

EFI_STATUS
EFIAPI
- GUID 0x22E0(
  VOID
);

EFI_STATUS
EFIAPI
- GUID 0x2280(
  VOID
);

EFI_STATUS
EFIAPI
Mask protocol (GUID at .rdata 0x2240)(
  VOID
);

EFI_STATUS
EFIAPI
*gDebugMaskProtocol;        // 0x23F0(
  VOID
);

EFI_STATUS
EFIAPI
data pointer and size (returned from SIO protocol Open at 3:7:9)(
  VOID
);

EFI_STATUS
EFIAPI
*gSioDataPtr;       // 0x2380(
  VOID
);

EFI_STATUS
EFIAPI
//(
  VOID
);

EFI_STATUS
EFIAPI
list pointer (from DXE HOB Library)(
  VOID
);

EFI_STATUS
EFIAPI
*gHobList;          // 0x23F8(
  VOID
);

EFI_STATUS
EFIAPI
communication buffer (32 bytes, allocated at entry)(
  VOID
);

EFI_STATUS
EFIAPI
*gCommunicationBuffer;  // 0x2388(
  VOID
);

EFI_STATUS
EFIAPI
PCI MMIO base address (calculated from PCI BAR)(
  VOID
);

EFI_STATUS
EFIAPI
gSioPciMmioBase;    // 0x2438(
  VOID
);

EFI_STATUS
EFIAPI
MMIO address and limit (from InitPchRcConfiguration)(
  VOID
);

EFI_STATUS
EFIAPI
gSioMmioAddress;    // 0x23B8(
  VOID
);

EFI_STATUS
EFIAPI
Configuration structure (44 bytes at 0x2440)(
  VOID
);

EFI_STATUS
EFIAPI
gUartConfig;(
  VOID
);

EFI_STATUS
EFIAPI
baud rate reference (1843200 = 115200 * 16)(
  VOID
);

EFI_STATUS
EFIAPI
gDefaultBaudRate;   // 0x23A0(
  VOID
);

EFI_STATUS
EFIAPI
flags(
  VOID
);

EFI_STATUS
EFIAPI
gSioSetupDone;                // 0x2398(
  VOID
);

EFI_STATUS
EFIAPI
BOOLEAN                gPchRcConfigured;             // 0x2371(
  VOID
);

EFI_STATUS
EFIAPI
BOOLEAN                gInitDone;                    // 0x2360(
  VOID
);

EFI_STATUS
EFIAPI
configuration flags (bitfield)(
  VOID
);

EFI_STATUS
EFIAPI
gUartConfigFlags;   // 0x239C(
  VOID
);

EFI_STATUS
EFIAPI
UART config fields(
  VOID
);

EFI_STATUS
EFIAPI
gWord2444;          // 0x2444(
  VOID
);

EFI_STATUS
EFIAPI
structures for HOB matching(
  VOID
);

EFI_STATUS
EFIAPI
gHobGuid1;          // 0x22F0(
  VOID
);

EFI_STATUS
EFIAPI
//=============================================================================(
  VOID
);

EFI_STATUS
EFIAPI
Functions(
  VOID
);

EFI_STATUS
EFIAPI
to DebugMaskProtocol DebugPrint handler(
  VOID
);

EFI_STATUS
EFIAPI
DebugMaskProtocol.AssertCallback (at offset 8)(
  VOID
);

EFI_STATUS
EFIAPI
I/O Helpers(
  VOID
);

EFI_STATUS
EFIAPI
serial config from variable data (baud, data bits, stop(
  VOID
);

EFI_STATUS
EFIAPI
gUartConfigFlags, gUartConfig, gXmmword2450, gQword2460(
  VOID
);

EFI_STATUS
EFIAPI
register width field.(
  VOID
);

EFI_STATUS
EFIAPI
EFI_SUCCESS;(
  VOID
);

EFI_STATUS
EFIAPI
Divisor Latch Access Bit (DLAB = 0x80)(
  VOID
);

EFI_STATUS
EFIAPI
divisor low/high, then clear DLAB(
  VOID
);

EFI_STATUS
EFIAPI
(Config->DataBuffer != NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
(Config->RegisterWidth == 4) {(
  VOID
);

EFI_STATUS
EFIAPI
I/O port write(
  VOID
);

EFI_STATUS
EFIAPI
((UINT16)Config->IoPort + 3, 0x80);(
  VOID
);

EFI_STATUS
EFIAPI
loc_40E is 0, return EFI_NOT_STARTED.(
  VOID
);

EFI_STATUS
EFIAPI
to read the "PchRcConfiguration" variable (size 1495).(
  VOID
);

EFI_STATUS
EFIAPI
variable has config bytes 83 and 197 set to 1:(
  VOID
);

EFI_STATUS
EFIAPI
gSioPciMmioBase = gSioMmioAddress + *(UINT16*)(gSioMmioAddress + 11)(
  VOID
);

EFI_STATUS
EFIAPI
UART config from MMIO to gUartConfig(
  VOID
);

EFI_STATUS
EFIAPI
PCI config space at offset 8(
  VOID
);

EFI_STATUS
EFIAPI
= gSioProtocol->OpenPciConfig (8, &Offset);(
  VOID
);

EFI_STATUS
EFIAPI
for $SBC signature, write config(
  VOID
);

EFI_STATUS
EFIAPI
(SearchPtr = Offset; SearchPtr < 0xF0000; SearchPtr++) {(
  VOID
);

EFI_STATUS
EFIAPI
back the offset(
  VOID
);

EFI_STATUS
EFIAPI
= gSioProtocol->WritePciConfig (8, &Offset);(
  VOID
);

EFI_STATUS
EFIAPI
for $SBF signature, write same config(
  VOID
);

EFI_STATUS
EFIAPI
PCI config space(
  VOID
);

EFI_STATUS
EFIAPI
notification GUID(
  VOID
);

EFI_STATUS
EFIAPI
Driver Functions(
  VOID
);

EFI_STATUS
EFIAPI
SMM SW Dispatch 2 Protocol(
  VOID
);

EFI_STATUS
EFIAPI
(gSmmSwDispatch2Protocol == NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
(!gInitDone) {(
  VOID
);

EFI_STATUS
EFIAPI
SIO UART registers and register with SMM SW Dispatch 2(
  VOID
);

EFI_STATUS
EFIAPI
(!gSmmReadyToBootRegistered ||(
  VOID
);

EFI_STATUS
EFIAPI
first SMI handler(
  VOID
);

EFI_STATUS
EFIAPI
second SMI handler (different SwSmiInputValue)(
  VOID
);

EFI_STATUS
EFIAPI
unregister action (SwSmiConfig[0] = 2)(
  VOID
);

EFI_STATUS
EFIAPI
(SwSmiConfig, sizeof (SwSmiConfig));(
  VOID
);

EFI_STATUS
EFIAPI
the ReadyToBoot callback immediately(
  VOID
);

EFI_STATUS
EFIAPI
((EFI_STATUS (*)(VOID *))gSmmReadyToBootProtocol)(gSmmReadyToBootProtocol);(
  VOID
);

EFI_STATUS
EFIAPI
if in SMM and SMM state != 3(
  VOID
);

EFI_STATUS
EFIAPI
= gSmmBase2Protocol->InSmm (&InSmm);(
  VOID
);

EFI_STATUS
EFIAPI
ReadyToBoot callback(
  VOID
);

EFI_STATUS
EFIAPI
SmmReadyToBootCallbackRegister ();(
  VOID
);

EFI_STATUS
EFIAPI
Point(
  VOID
);

EFI_STATUS
EFIAPI
protocol pointers(
  VOID
);

EFI_STATUS
EFIAPI
= SystemTable;(
  VOID
);

EFI_STATUS
EFIAPI
SMM communication buffer (32 bytes, EfiReservedMemoryType)(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->AllocatePool ((
  VOID
);

EFI_STATUS
EFIAPI
SIO Protocol (open with params 3, 7, 9)(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->LocateProtocol (&gSioProtocolGuid, NULL, &gSioProtocol);(
  VOID
);

EFI_STATUS
EFIAPI
protocol notification for SMM Ready To Boot(
  VOID
);

EFI_STATUS
EFIAPI
= NULL;(
  VOID
);

EFI_STATUS
EFIAPI
SMM Base 2 periodic callback via SetTimer (period = 8)(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->SetTimer ((
  VOID
);

EFI_STATUS
EFIAPI
protocol notification for SMM SW Dispatch 2(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->RegisterProtocolNotify ((
  VOID
);

EFI_STATUS
EFIAPI
protocol notification for SMM Dispatch 2 data(
  VOID
);

EFI_STATUS
EFIAPI
(DXE standard entry, supplied by lib)(
  VOID
);

EFI_STATUS
EFIAPI
by UefiBootServicesTableLib + UefiRuntimeServicesTableLib.(
  VOID
);

EFI_STATUS
EFIAPI
ImageHandle, gST, gBS, gRT globals, calls GetSystemHobList(
  VOID
);

EFI_STATUS
EFIAPI
invokes LegacySredirDriverEntryPoint.(
  VOID
);

#endif /* __LEGACYSREDIR_H__ */