| Address | Name | Description |
|---|---|---|
| PciHbNotifyPhase | ||
| PciHbGetNextRootBridge | ||
| PciHbGetAllocAttributes | ||
| PciHbStartBusEnumeration | ||
| PciHbSetBusNumbers | ||
| PciHbSubmitResources | ||
| PciHbGetProposedResources | ||
| PciHbPreprocessController | ||
| ModuleEntryPoint | ||
| PciHostBridgeEntry | ||
| PciHostBridgeReserveCspResources | ||
| PciHostBridgeSetupConfig | ||
| PciHostBridgeConvertMemory | ||
| LocateDxeServicesTable | ||
| LocateBoardInfo2Protocol | ||
| PciHostBridgeFindSdlRecordIndex | ||
| PciHostBridgeGetRootBridges | ||
| Global | Variables | |
| UEFI | BootServices / Runtime / DXE core handles (initialized in sub_3BC) | |
| EFI_HANDLE | gImageHandle = NULL; // sub_3BC saves ImageHandle | |
| sub_3BC | saves SystemTable | |
| sub_3BC | saves BS | |
| sub_3BC | saves RT | |
| DXE | Services (qword_184F0) | |
| Host | bridge tracking | |
| qword_18450 | -- number of host bridges | |
| qword_18428 | -- allocated HB private data array (168 bytes per entry) | |
| UINT64 | gHostBrgCount = 0; | |
| MM | PCI USRA handle (PCIE_SEG_BUS_TABLE / MMIO PCI cfg access) | |
| qword_184F8 | // | |
| PCD | protocol (qword_18480) | |
| VOID | *gpPcdProtocol = NULL; | |
| AMI_BOARD_INFO2_PROTOCOL | (qword_18488) | |
| Contains | SDL (System Description Layer) board data | |
| VOID | *gpBoardInfo2Protocol = NULL; | |
| SDL | host bridge data pointer (from BoardInfo2 protocol) | |
| Setup | configuration buffer (from UEFI variable "Setup") | |
| qword_1BBB8 | -- 7 bytes: [0]=PciHot, [1]=PciAer, [2]=PciHpc, [3]=Above4G, [4-5]=? | |
| VOID | *gpSetupConfig = NULL; | |
| gEdkiiIoMmuProtocol | (qword_18430) | |
| VOID | *gpIoMmuProtocol = NULL; | |
| AmiBoardPciInitProtocol | (qword_18420) | |
| VOID | *gpAmiBoardPciInit = NULL; | |
| ReadyToBoot | event handle (qword_18560) | |
| EFI_EVENT | gReadyToBootEvent = NULL; | |
| SMM | Handoff data (qword_18440 / qword_18438) | |
| UINT64 | gSmmHandoffHostCnt = 0; | |
| Local | function declarations (renamed from sub_XXXX) | |
| Standard | library init function | saves boot services/runtime/dxe tables |
| static | EFI_STATUS | |
| Protocol | dispatch function declarations (HB protocol) | |
| EFI_STATUS | EFIAPI | |
| UEFI | DXE driver entry point. Called by firmware. | |
| Delegates | to PciHostBridgeEntry(). | |
| Saves | globals: ImageHandle, gST, gBS, gRT, gDS, also initializes | |
| PCIE_SEG_BUS_TABLE | and PCD library. Called once at entry. | |
| Save | UEFI core handles | |
| Locate | DXE Services Table (gDS) | |
| Status | = EfiGetSystemConfigurationTable(&gEfiDxeServicesTableGuid, &gDS); | |
| Locate | PCD protocol (mPcd) | |
| Status | = gBS->LocateProtocol(&gPcdProtocolGuid, NULL, &gpPcdProtocol); | |
| Locate | MM PCI USRA (PCIE_SEG_BUS_TABLE) | |
| Status | = gBS->LocateProtocol(&gAmiPcieSegBusTableGuid, NULL, &gpPciUsra); | |
| Validate | PCIE_SEG_BUS_TABLE size is sufficient | |
| Main | driver logic. The entry function: | |
| module version banner | ||
| DEBUG | ((EFI_D_INFO | |
| Locate | AMI_BOARD_INFO2_PROTOCOL to get SDL host bridge data | |
| Status | = LocateBoardInfo2Protocol (); | |
| Count | active host bridges (SDL records with bit[57] & 1 set) | |
| ActiveCount | = 0; | |
| Allocate | array of active HB SDL record pointers | |
| will | be overwritten | |
| Reserve | chipset-specific (CSP) resources | |
| DEBUG | ((EFI_D_INFO, " HB: Reserve CSP Resources( ImageHandle=0x%X)\n", ImageHandle)); | |
| Allocate | global resources: setup config (7 bytes), HB private array | |
| gpSetupConfig | = AllocateZeroPool (7); | |
| Read | platform setup config from UEFI "Setup" variable | |
| Status | = PciHostBridgeSetupConfig (); | |
| Convert | all unallocated memory to MMIO using GCD services | |
| Status | = PciHostBridgeConvertMemory (ImageHandle); | |
| Locate | AmiBoardPciInitProtocol (for board-specific PCI init callbacks) | |
| if | (gpAmiBoardPciInit == NULL) { | |
| Iterate | over each active host bridge | |
| for | (HostBrgIndex = 0; HostBrgIndex < gHostBrgCount; HostBrgIndex++) { | |
| Get | SDL record index for this host bridge | |
| if | (SdlRecord != NULL) { | |
| Fill | in HB private context | |
| Set | attributes supported: | |
| Install | protocol dispatch function table | |
| Conditionally | disable above-4G decode attribute | |
| if | (!((UINT8*)gpSetupConfig)[3]) { | |
| Call | chipset-specific common function: Initialize HB (Step 12, Cmd 1) | |
| Status | = PciHostBridgeCallCmnFn (Private, 12, 1); | |
| Install | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL protocol | |
| Status | = gBS->InstallProtocolInterface ( | |
| Get | root bridges for this host bridge from SDL | |
| Status | = PciHostBridgeGetRootBridges ( | |
| Accumulate | per-previous-host RB counts for UID assignment | |
| if | (HostBrgIndex > 0) { | |
| If | no root bridges found, skip HB processing | |
| if | (RbCount == 0) { | |
| For | each root bridge found, allocate and initialize a root bridge | |
| private | context of 480 bytes. | |
| for | (RbIndex = 0; RbIndex < RbCount; RbIndex++) { | |
| Allocate | root bridge context (480 bytes total) | |
| RbPrivate | = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_PRIVATE)); | |
| Populate | root bridge: link to host bridge, get SDL record, etc. | |
| Get | SDL record index for this root bridge | |
| if | (RbSdlRecord != NULL) { | |
| Attributes | supported: from SDL entry offset 16 | |
| ASL | name buffer: from SDL entry offset 24 | |
| If | above-4G decode is enabled (setup[3] true), add 4G decode attribute | |
| if | (((UINT8*)gpSetupConfig)[3]) { | |
| Call | chipset-specific: Initialize RB (Step 13, Cmd 2) | |
| Status | = PciHostBridgeCallCmnFn (RbPrivate, 13, 2); | |
| If | RB is flagged as NOT present, skip further initialization | |
| if | ((UINT8)((UINT8*)RbPrivate + 243)) { | |
| Install | protocol dispatch table for RootBridgeIo | |
| Save | segment number from SDL | |
| Build | initial bus range ACPI descriptor (46 bytes) | |
| Fill | QWord Resource Descriptor: | |
| type | = 0x8A (Small: 0x8A is QWord descriptor for bus range) | |
| length | = 43 | |
| _MIN | = secondary bus number (RbSdlRecord[8]) | |
| _MAX | = subordinate bus number (from next SDL or 0xFF) | |
| _LEN | = _MAX - _MIN + 1 | |
| QWord | Address Space Descriptor | |
| length | BusDescriptor[2] = 2; // bus range type | |
| _MIN | (UINT64)(BusDescriptor + 22) = 0xFF; // _MAX (may be adjusted if next bridge) | |
| _LEN | } | |
| Call | chipset-specific: Initialize Bus Range (Step 14, Cmd 2) | |
| BusMinOld | = (UINT16)(RbPrivate->BusDescriptor + 14); | |
| Create | ACPI device path (_SB scope H[host]R RbBSH ) | |
| and | install it via RuntimeServices->SetVariable or similar | |
| Append | bus descriptor to RB resource list | |
| Status | = PciRootBridgeAppendResource (RbPrivate, BusDescriptor); | |
| Allocate | and install DEVICE_PATH protocol with ACPI _UID | |
| HID | (UINT32)((UINT8*)PathData + 4) = 0x0A034810; // UID | |
| UID | + end | |
| Install | both RB_IO and DevicePath protocols together | |
| Status | = gBS->InstallMultipleProtocolInterfaces ( | |
| RbIo | protocol | |
| Device | path | |
| If | hot-plug controller support is enabled (setup[2] == 1) | |
| install | HPC (Hot-Plug Controller) protocol | |
| if | (((UINT8*)gpSetupConfig)[2] == 1) { | |
| end | for each root bridge | |
| end | for each host bridge | |
| Install | SMM Handoff protocol if not already installed | |
| if | (gSmmHandoffHandle == NULL) { | |
| Create | ReadyToBoot event | |
| Status | = gBS->CreateEvent ( | |
| Register | IOMMU protocol notification and close SMM lock event | |
| Status | = PciAccessCspRegisterIoMmuNotify ( | |
| Check | for IOMMU protocol (gEdkiiIoMmuProtocolGuid) | |
| if | (gpIoMmuProtocol == NULL) { | |
| Uses | GCD services to: | |
| Called | before HB private data is installed. | |
| Get | DXE services table | |
| DxeStatus | = LocateDxeServicesTable (); | |
| Iterate | over each SDL host bridge entry, walk its memory resources | |
| and | mark them in GCD. For each entry: | |
| Implementation | detail: This function processes 342-byte SDL records | |
| looking | at IOBase, MemBase, MemLen fields. | |
| return | EFI_SUCCESS; | |
| Reads | the UEFI "Setup" variable (which is an EFI variable with the | |
| platform | setup configuration GUID) to extract PCI-related setup options | |
| into | a 7-byte global buffer (gpSetupConfig): | |
| If | the "Setup" variable can't be read, defaults are set: | |
| Read | "Setup" variable (the platform setup variable) | |
| Status | = gRT->GetVariable ( | |
| Variable | not found; use defaults | |
| Uses | the DXE memory services to: | |
| Also | handles the IO space in a similar manner. | |
| Called | after CSP resource reservation. | |
| Walk | GCD memory map entries: | |
| For | each entry that is free (unallocated) and within the | |
| host | bridge's resource windows: | |
| Library | Helpers (internal) | |
| AllocatePool | (original sub_47D8 @ 0x47D8) | |
| AllocateZeroPool | (original sub_4804 @ 0x4804) | |
| GetPcdProtocol | (original sub_35D0 @ 0x35D0) | |
| EfiGetSystemConfigurationTable | (original sub_4510 @ 0x4510) | |
| Walk | the configuration table looking for the matching GUID | |
| for | (i = 0; i < EntryCount; i++) { | |
| LocateDxeServicesTable | (original sub_4B5C @ 0x4B5C) | |
| EFI_STATUS | LocateDxeServicesTable ( | |
| LocateBoardInfo2Protocol | (original sub_365C @ 0x365C) | |
| EFI_STATUS | LocateBoardInfo2Protocol ( | |
| PciHostBridgeFindSdlRecordIndex | (original sub_3754 @ 0x3754) | |
| EFI_STATUS | PciHostBridgeFindSdlRecordIndex ( | |
| PciHostBridgeGetRootBridges | (original sub_37D0 @ 0x37D0) | |
| EFI_STATUS | PciHostBridgeGetRootBridges ( | |
| Count | entries that belong to this bridge index (SDL[0]==BridgeIndex) | |
| Allocate | and fill output list | |
| OutputList | = (UINT64)AllocatePool (8 FoundEntries); |
Generated by HR650X BIOS Decompilation Project