CpuCsrAccessSMM

Function Table

Address	Name	Description
	IoRead32
	UsraRead
	UsraWrite
	UsraWriteCmdOnly
	MmioRead
	MmioWrite
	PcuMailboxCmd
	VcuMailboxCmd
	CpuCsrConfigInit
	GetSocketConfig
	CpuCsrAccessSmmHandler
	CpuCsrAccessSmmEntryPoint
This	SMM driver provides a protocol-based interface for accessing CPU
uncore	Control and Status Registers (CSRs), PCIe configuration space
and	PCU/VCU mailbox registers across sockets on the Purley platform.
The	driver exports 12 handler functions through a dispatch table registered
via	SmiHandlerRegister. The dispatch is indexed by sub-command:
An	internal function (sub_DA4) reloads per-socket config data from the
large	SysHost structure during initialization.
GUIDs	// ------------------------------------------------------------------------
SMM	handler: {0067835F-9A50-433A-8CBB-852078197814}
USRA	protocol (CpRcPkg): {FD480A76-B134-4EF7-ADFE-B0E054639807}
PCIe	RootBridge: {A7CED760-C71C-4E1A-ACB1-89604D5216CB}
Global	Variables (.data segment)
0x4180	*VOID gSmmCsrProtocol; // 0x4188**
0x4190	*UINT8 gCsrConfigCache; // 0x4198**
0x41A0	*EFI_BOOT_SERVICES gBS; // 0x41A8**
0x41B0	*EFI_RUNTIME_SERVICES gRT; // 0x41B8**
0x41C0	*VOID gSmmStatusCode; // 0x41C8**
0x41D0	*VOID gHobList; // 0x41D8**
0x41E0	*VOID gPcd; // 0x41E8**
0x4300	*UINT64 gCsrData; // 0x4308**
0x4310	*UINT64 gSmramRanges; // 0x4318**
0x4320	// Per-socket config cache
0x4340	UINT8 gSocketChaMap[24]; // 0x4344
0x435C	UINT8 gSocketData2[4]; // 0x4364
0x4368	UINT8 gCpuType; // 0x436C
0x436D	UINT32 gSocketEnableMask; // 0x436E
0x4372	UINT32 gMmioBaseShift; // 0x4376
0x437A	UINT8 gSocketChPerInst[24]; // 0x4385
0x4408	UINT32 gLastCheckpointCode; // 0x4410
USRA	wrappers
MMIO	address translation
Mailbox	helpers
Box	routing (sub_20A4)
SMI	handler dispatch entry

Generated by HR650X BIOS Decompilation Project