/** @file
  IioInit.h -- Header for IioInit

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __IIOINIT_H__
#define __IIOINIT_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
IioInitAssert(
  VOID
);

EFI_STATUS
EFIAPI
IioInitGetMmPciBaseProtocol(
  VOID
);

EFI_STATUS
EFIAPI
IioInitGetStackProtocol(
  VOID
);

EFI_STATUS
EFIAPI
ModuleEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
EFI protocol pointers(
  VOID
);

EFI_STATUS
EFIAPI
ImageHandle     = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
IIO data(
  VOID
);

EFI_STATUS
EFIAPI
byte_DD59  = 0;          // S3 boot script flag(
  VOID
);

EFI_STATUS
EFIAPI
token for PcdIioRevision(
  VOID
);

EFI_STATUS
EFIAPI
token for PcdIioPostInitDone(
  VOID
);

EFI_STATUS
EFIAPI
script label pointer(
  VOID
);

EFI_STATUS
EFIAPI
script label entry(
  VOID
);

EFI_STATUS
EFIAPI
table(
  VOID
);

EFI_STATUS
EFIAPI
width/stride table: byte pairs of (element_size, stride_size) for(
  VOID
);

EFI_STATUS
EFIAPI
widths 0..3, plus two more entries at +16 for the receive stride.(
  VOID
);

EFI_STATUS
EFIAPI
byte_A7C0[32] = { 0 };(
  VOID
);

EFI_STATUS
EFIAPI
definitions for IIO protocols(
  VOID
);

EFI_STATUS
EFIAPI
gIioStackProtocolGuid  = { 0x0 };  // unk_AA70 - IIO Stack Protocol(
  VOID
);

EFI_STATUS
EFIAPI
- MM PCIe Base Protocol(
  VOID
);

EFI_STATUS
EFIAPI
- PCD Protocol(
  VOID
);

EFI_STATUS
EFIAPI
declarations of static helper functions(
  VOID
);

EFI_STATUS
EFIAPI
VOID(
  VOID
);

EFI_STATUS
EFIAPI
/ Debug helper(
  VOID
);

EFI_STATUS
EFIAPI
initialization core (entry logic)(
  VOID
);

EFI_STATUS
EFIAPI
image handle and system table globally(
  VOID
);

EFI_STATUS
EFIAPI
= ImageHandleParam;(
  VOID
);

EFI_STATUS
EFIAPI
boot services and runtime services tables(
  VOID
);

EFI_STATUS
EFIAPI
= SystemTable->BootServices;(
  VOID
);

EFI_STATUS
EFIAPI
the DxeServicesTable (gDS)(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->LocateProtocol (&gDxeServicesTableGuid(
  VOID
);

EFI_STATUS
EFIAPI
initialization(
  VOID
);

EFI_STATUS
EFIAPI
(EFI_ERROR (Status)) {(
  VOID
);

EFI_STATUS
EFIAPI
the MM PCIe Base protocol(
  VOID
);

EFI_STATUS
EFIAPI
(mPciUsra == NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
();(
  VOID
);

EFI_STATUS
EFIAPI
PCD interface and read IIO revision token(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT64)GetPcdProtocol ();(
  VOID
);

EFI_STATUS
EFIAPI
IIO revision and optionally fix up IioRevision(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT8 *)PcdGetPtr (PcdIioRevision);(
  VOID
);

EFI_STATUS
EFIAPI
interrupt state then call initialization routines(
  VOID
);

EFI_STATUS
EFIAPI
= SaveAndDisableInterrupts ();(
  VOID
);

EFI_STATUS
EFIAPI
loop for timestamp to advance (small delay)(
  VOID
);

EFI_STATUS
EFIAPI
(((Timestamp + 357 - (UINT32)ReadTimestamp ()) & 0x800000) == 0) {(
  VOID
);

EFI_STATUS
EFIAPI
interrupt state(
  VOID
);

EFI_STATUS
EFIAPI
(InterruptsEnabled) {(
  VOID
);

EFI_STATUS
EFIAPI
protocols / call main IIO initialization chain(
  VOID
);

EFI_STATUS
EFIAPI
= IioInitEntry ();(
  VOID
);

EFI_STATUS
EFIAPI
that IIO post-init is done(
  VOID
);

EFI_STATUS
EFIAPI
Stack access helpers(
  VOID
);

EFI_STATUS
EFIAPI
Protocol helper(
  VOID
);

EFI_STATUS
EFIAPI
script S3 support(
  VOID
);

EFI_STATUS
EFIAPI
/ VT-d initialization(
  VOID
);

EFI_STATUS
EFIAPI
port configuration(
  VOID
);

EFI_STATUS
EFIAPI
current hot-plug and link status registers(
  VOID
);

EFI_STATUS
EFIAPI
= StackProtocol->Read (SocketIndex, 0, PCIE_HP_REG);(
  VOID
);

EFI_STATUS
EFIAPI
hot-plug detect on this port(
  VOID
);

EFI_STATUS
EFIAPI
= HotPlugReg | 1;(
  VOID
);

EFI_STATUS
EFIAPI
slot capability(
  VOID
);

EFI_STATUS
EFIAPI
back link control registers(
  VOID
);

EFI_STATUS
EFIAPI
= LinkStatusReg;(
  VOID
);

EFI_STATUS
EFIAPI
sub-class from class code register(
  VOID
);

EFI_STATUS
EFIAPI
= StackProtocol->Read (SocketIndex, StackId, PCIE_CLASS_REG);(
  VOID
);

EFI_STATUS
EFIAPI
IOAPIC redirection for all 8 ports(
  VOID
);

EFI_STATUS
EFIAPI
(PortIndex = 0; PortIndex < 8; PortIndex++) {(
  VOID
);

EFI_STATUS
EFIAPI
MMCFG / Address library routines (from PcieCommonInitLib / PcieAddressLib)(
  VOID
);

EFI_STATUS
EFIAPI
address translation (from PcieAddressLib / CpRcPkg)(
  VOID
);

EFI_STATUS
EFIAPI
element size to 1 for access widths 4..7(
  VOID
);

EFI_STATUS
EFIAPI
(AccessWidth - 4 <= 3) {(
  VOID
);

EFI_STATUS
EFIAPI
alignment(
  VOID
);

EFI_STATUS
EFIAPI
= byte_A7C0[WidthIndex];(
  VOID
);

EFI_STATUS
EFIAPI
address range(
  VOID
);

EFI_STATUS
EFIAPI
(Count > 0) {(
  VOID
);

EFI_STATUS
EFIAPI
buffer alignment(
  VOID
);

EFI_STATUS
EFIAPI
that MMCFG table fits in PCD-allocated space(
  VOID
);

EFI_STATUS
EFIAPI
(sub_CF0 () && TotalSize >= (UINTN)PcdProtocol->GetSize (6)) {(
  VOID
);

EFI_STATUS
EFIAPI
base address not provided, use PCD default(
  VOID
);

EFI_STATUS
EFIAPI
(!TableHeader->OemId && !TableHeader->Reserved) {(
  VOID
);

EFI_STATUS
EFIAPI
Entry Point(
  VOID
);

#endif /* __IIOINIT_H__ */