FpgaLoaderPeim

Overview

This PEIM loads FPGA bitstreams via MRC (Memory Reference Code) hook PPIs during early PEI phase. It manages MP services for BSP/AP coordination, performs per-socket FPGA programming with retry logic (max 3 attempts), powers off unused FPGA sockets, and triggers a warm reset after successful programming. On subsequent boots (FPGA already active), it locks the FPGA configuration via FpgaPeiLock.

Key Functions

• FpgaLoaderEntry -- Main entry point orchestrating the full FPGA load flow.
• FpgaConfigurationGetValues -- Reads or creates FPGA configuration HOB.
• FpgaGetPcdProtocol -- Obtains PCD protocol for platform settings.
• FpgaMpServicesData -- Enumerates processors and finds the BSP socket.
• FpgaLoadBitstream -- Per-socket FPGA bitstream loading with retry.
• FpgaConfigurationSetValues -- Persists updated configuration to HOB.
• FpgaDisableUnusedSockets -- Powers off unpopulated FPGA sockets.
• FpgaPeiLock -- Locks FPGA configuration on subsequent boots.

Dependencies

• Chip Services PPI
• MP Services PPI (BSP/AP coordination)
• Core Services PPI
• PCD Protocol
• MRC Hooks PPIs

Platform

• Architecture: IA32 (x86, PE32)
• Source: Intel Purley platform FPGA initialization
• Base address: 0xFFD68CE4
• Total functions: 41