/** @file
  SiInitPreMem.h -- Header for SiInitPreMem

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __SIINITPREMEM_H__
#define __SIINITPREMEM_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
PchResetInitCallback(
  VOID
);

EFI_STATUS
EFIAPI
PchResetCallback2(
  VOID
);

EFI_STATUS
EFIAPI
SetupTraceHubFwBar(
  VOID
);

EFI_STATUS
EFIAPI
IsPchSkuSupported(
  VOID
);

EFI_STATUS
EFIAPI
IsDwrDetected(
  VOID
);

EFI_STATUS
EFIAPI
GetPerformanceLogBuffer(
  VOID
);

EFI_STATUS
EFIAPI
RecordPerformanceEntry(
  VOID
);

EFI_STATUS
EFIAPI
DebugPrint(
  VOID
);

EFI_STATUS
EFIAPI
PpiInstall(
  VOID
);

EFI_STATUS
EFIAPI
StartPerformanceMeasurement(
  VOID
);

EFI_STATUS
EFIAPI
EndPerformanceMeasurement(
  VOID
);

EFI_STATUS
EFIAPI
SiInitPreMemEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
SiInitPrePolicy(
  VOID
);

EFI_STATUS
EFIAPI
PrintPchInfo(
  VOID
);

EFI_STATUS
EFIAPI
PchWdtInit(
  VOID
);

EFI_STATUS
EFIAPI
PchWdtIsUnexpectedReset(
  VOID
);

EFI_STATUS
EFIAPI
InstallPchResetPpi(
  VOID
);

EFI_STATUS
EFIAPI
InstallPchSpiPpi(
  VOID
);

EFI_STATUS
EFIAPI
PchInitPreMem(
  VOID
);

EFI_STATUS
EFIAPI
PchAcpiBaseSet(
  VOID
);

EFI_STATUS
EFIAPI
PchPwrmBaseGet(
  VOID
);

EFI_STATUS
EFIAPI
PchPwrmBaseSet(
  VOID
);

EFI_STATUS
EFIAPI
PchTcoBaseSet(
  VOID
);

EFI_STATUS
EFIAPI
PchFabricErrorCheck(
  VOID
);

EFI_STATUS
EFIAPI
PchEarlyDisabledDeviceHandling(
  VOID
);

EFI_STATUS
EFIAPI
GpioInitEarly(
  VOID
);

EFI_STATUS
EFIAPI
MmioRead16(
  VOID
);

EFI_STATUS
EFIAPI
MmioWrite16(
  VOID
);

EFI_STATUS
EFIAPI
PchGetMmPciAddress(
  VOID
);

EFI_STATUS
EFIAPI
PchPciRead16(
  VOID
);

EFI_STATUS
EFIAPI
PchPciWrite32(
  VOID
);

EFI_STATUS
EFIAPI
PchPcrRead32(
  VOID
);

EFI_STATUS
EFIAPI
PchPcrWrite32(
  VOID
);

EFI_STATUS
EFIAPI
SpiProtocolInit(
  VOID
);

EFI_STATUS
EFIAPI
PchInfoGetPchSeriesStr(
  VOID
);

EFI_STATUS
EFIAPI
PchInfoGetPchSteppingStr(
  VOID
);

EFI_STATUS
EFIAPI
PchInfoGetPchSkuStr(
  VOID
);

EFI_STATUS
EFIAPI
7 (0x80) indicates SiInitPrePolicy has already been called.(
  VOID
);

EFI_STATUS
EFIAPI
UINT8  *mSiInitPolicyDoneFlag = (UINT8 *)0xFA044;(
  VOID
);

EFI_STATUS
EFIAPI
log entry type: the entry point records 0x50E0 as the event(
  VOID
);

EFI_STATUS
EFIAPI
(20704 decimal) for the SiInitPrePolicy performance measurement.(
  VOID
);

EFI_STATUS
EFIAPI
global PEI services pointer (maintained across calls)(
  VOID
);

EFI_STATUS
EFIAPI
EFI_PEI_SERVICES **mPeiServices = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
declarations of internal sub-functions(
  VOID
);

EFI_STATUS
EFIAPI
Services helper: sub_FFD8AD54 / GetPeiServicesPtr(
  VOID
);

EFI_STATUS
EFIAPI
the PEI Services PPI pointer. The implementation reads from(
  VOID
);

EFI_STATUS
EFIAPI
IDT-based PEI Services Table Pointer.(
  VOID
);

EFI_STATUS
EFIAPI
**(
  VOID
);

EFI_STATUS
EFIAPI
Output: sub_FFD7F97E / GetDebugInterface(
  VOID
);

EFI_STATUS
EFIAPI
the ReportStatusCode PPI (GUID: 36232936-0E76-31C8-...)(
  VOID
);

EFI_STATUS
EFIAPI
caches it for use by DebugPrint.(
  VOID
);

EFI_STATUS
EFIAPI
REPORT_STATUS_CODE_PPI *(
  VOID
);

EFI_STATUS
EFIAPI
Print: sub_FFD7F9AF(
  VOID
);

EFI_STATUS
EFIAPI
debug print via ReportStatusCode PPI.(
  VOID
);

EFI_STATUS
EFIAPI
emits if the requested error level matches the current debug mask.(
  VOID
);

EFI_STATUS
EFIAPI
with:(
  VOID
);

EFI_STATUS
EFIAPI
(0x40 = 64)   for normal trace messages(
  VOID
);

EFI_STATUS
EFIAPI
(0x80000000)  for error/assert messages(
  VOID
);

EFI_STATUS
EFIAPI
EFIAPI(
  VOID
);

EFI_STATUS
EFIAPI
if the current debug level has this ErrorLevel enabled.(
  VOID
);

EFI_STATUS
EFIAPI
debug mask is read from a global variable.(
  VOID
);

EFI_STATUS
EFIAPI
= GetDebugMask ();(
  VOID
);

EFI_STATUS
EFIAPI
Install: sub_FFD7F948(
  VOID
);

EFI_STATUS
EFIAPI
wrapper: PeiServices->InstallPpi(PpiList)(
  VOID
);

EFI_STATUS
EFIAPI
Log: sub_FFD7FBC7 / sub_FFD7FC48(
  VOID
);

EFI_STATUS
EFIAPI
a TSC-based performance entry. Uses a buffer tracked via(
  VOID
);

EFI_STATUS
EFIAPI
that returns a log array.(
  VOID
);

EFI_STATUS
EFIAPI
VOID(
  VOID
);

EFI_STATUS
EFIAPI
the HOB-based performance log buffer. If no HOB exists(
  VOID
);

EFI_STATUS
EFIAPI
Entry Point: _ModuleEntryPoint (0xffd7f7a1)(
  VOID
);

EFI_STATUS
EFIAPI
0: One-time initialization guard(
  VOID
);

EFI_STATUS
EFIAPI
bit 7 of the flag byte at mSiInitPolicyDoneFlag (0xFA044).(
  VOID
);

EFI_STATUS
EFIAPI
not set, mark as done. This is an anti-double-call protection.(
  VOID
);

EFI_STATUS
EFIAPI
((*mSiInitPolicyDoneFlag & BIT7) == 0) {(
  VOID
);

EFI_STATUS
EFIAPI
1: SiInitPrePolicy - Early silicon policy init (TraceHub)(
  VOID
);

EFI_STATUS
EFIAPI
(EFI_D_INFO, "SiInitPrePolicy() Start\n");(
  VOID
);

EFI_STATUS
EFIAPI
performance measurement(
  VOID
);

EFI_STATUS
EFIAPI
type = 20704 (0x50E0)(
  VOID
);

EFI_STATUS
EFIAPI
= AsmReadTsc ();(
  VOID
);

EFI_STATUS
EFIAPI
2a: PchInitPrePolicy - PCH identification(
  VOID
);

EFI_STATUS
EFIAPI
();(
  VOID
);

EFI_STATUS
EFIAPI
2b: PchInitPrePolicy - WDT, Reset, SPI, GPIO(
  VOID
);

EFI_STATUS
EFIAPI
3: Notify that SiInitPrePolicy is complete(
  VOID
);

EFI_STATUS
EFIAPI
= GetPeiServicesPtr ();(
  VOID
);

EFI_STATUS
EFIAPI
Intel TraceHub (chipset trace/debug hub) MMIO BARs.(
  VOID
);

EFI_STATUS
EFIAPI
TraceHub device is at PCI B:D:F 0:20:7 (D20:F7) on the PCH.(
  VOID
);

EFI_STATUS
EFIAPI
PCH power management base address(
  VOID
);

EFI_STATUS
EFIAPI
(&PchPwrmBase);(
  VOID
);

EFI_STATUS
EFIAPI
TraceHub device via PCH MMIO config (D20:F7 = B:D:F 0:20:7)(
  VOID
);

EFI_STATUS
EFIAPI
= (TRACEHUB_DEVICE *)(UINTN)PchGetMmPciAddress (0, 20, 7);(
  VOID
);

EFI_STATUS
EFIAPI
TraceHub presence (VID/DID = 0xFFFF means not present)(
  VOID
);

EFI_STATUS
EFIAPI
(MmioRead16 (&TraceHub->VendorId) == 0xFFFF) {(
  VOID
);

EFI_STATUS
EFIAPI
if TraceHub was already initialized (MSE bit)(
  VOID
);

EFI_STATUS
EFIAPI
((TraceHub->Command & BIT1) != 0) {(
  VOID
);

EFI_STATUS
EFIAPI
(EFI_D_INFO, "TraceHubInitialize() - Setting MTB_BAR\n");(
  VOID
);

EFI_STATUS
EFIAPI
(bit 1) is the minimum - enables MMIO for MTB only(
  VOID
);

EFI_STATUS
EFIAPI
MSE only initially(
  VOID
);

EFI_STATUS
EFIAPI
SCRPD0.24 to decide if SW/FW BARs should be programmed(
  VOID
);

EFI_STATUS
EFIAPI
= *((volatile UINT32 *)TRACE_HUB_SCRPD0_REG);(
  VOID
);

EFI_STATUS
EFIAPI
SW trace buffer frequency and BAR(
  VOID
);

EFI_STATUS
EFIAPI
disable to program BARs(
  VOID
);

EFI_STATUS
EFIAPI
FW_BAR (firmware trace buffer - at offset 0x20)(
  VOID
);

EFI_STATUS
EFIAPI
(EFI_D_INFO, "TraceHubInitialize() - Setting FW_BAR\n");(
  VOID
);

EFI_STATUS
EFIAPI
both MSE and BME for full TraceHub operation(
  VOID
);

EFI_STATUS
EFIAPI
(EFI_D_INFO, "TraceHubInitialize() - Enabling MSE and BME\n");(
  VOID
);

EFI_STATUS
EFIAPI
+ BME(
  VOID
);

EFI_STATUS
EFIAPI
(Self-Test Trace) disconnected - disable TraceHub(
  VOID
);

EFI_STATUS
EFIAPI
the TraceHub FW_BAR at PCI config space offset 0x20.(
  VOID
);

EFI_STATUS
EFIAPI
is mapped to 0xFE0C0000 with an 8KB window.(
  VOID
);

EFI_STATUS
EFIAPI
DMIC.SRL (DMIC is locked), read from PCR(
  VOID
);

EFI_STATUS
EFIAPI
= PchPcrRead32 (PID_PSF1, 4);(
  VOID
);

EFI_STATUS
EFIAPI
LPC device is present(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT32 *)(UINTN)PchGetMmPciAddress (0, 31, 0);(
  VOID
);

EFI_STATUS
EFIAPI
FW_BAR at PCI config offset 0x20 (expansion ROM BAR)(
  VOID
);

EFI_STATUS
EFIAPI
value 0xFE0C0000 (8KB).(
  VOID
);

EFI_STATUS
EFIAPI
PCH device information and logs it via DebugPrint.(
  VOID
);

EFI_STATUS
EFIAPI
PCH series (returns: 1 = LBG, 2 = SPX)(
  VOID
);

EFI_STATUS
EFIAPI
= PchGetSteppingInfo ();(
  VOID
);

EFI_STATUS
EFIAPI
series string(
  VOID
);

EFI_STATUS
EFIAPI
= sizeof (SeriesStr);(
  VOID
);

EFI_STATUS
EFIAPI
stepping string(
  VOID
);

EFI_STATUS
EFIAPI
= sizeof (SteppingStr);(
  VOID
);

EFI_STATUS
EFIAPI
SKU string(
  VOID
);

EFI_STATUS
EFIAPI
= sizeof (SkuStr);(
  VOID
);

EFI_STATUS
EFIAPI
= PchLbg (Lewisburg / PCH-H): IDs A1C0-A1CF, A243, A240-A24F(
  VOID
);

EFI_STATUS
EFIAPI
= PchSpx (Sphinx  / PCH-LP): IDs 9D40-9D43, 9D46, 9D48(
  VOID
);

EFI_STATUS
EFIAPI
LPC Device ID from D31:F0 offset +2(
  VOID
);

EFI_STATUS
EFIAPI
= MmioRead16 ((
  VOID
);

EFI_STATUS
EFIAPI
Lewisburg (LBG) range(
  VOID
);

EFI_STATUS
EFIAPI
((LpcDeviceId >= V_LBG_DEVICE_ID_MIN && LpcDeviceId <= V_LBG_DEVICE_ID_MAX) ||(
  VOID
);

EFI_STATUS
EFIAPI
Sphinx (SPX) range(
  VOID
);

EFI_STATUS
EFIAPI
if (LpcDeviceId == 0x9D40 || LpcDeviceId == 0x9D41 ||(
  VOID
);

EFI_STATUS
EFIAPI
WDT status from PCH and configures WDT control bits.(
  VOID
);

EFI_STATUS
EFIAPI
WDT status (BIT14)(
  VOID
);

EFI_STATUS
EFIAPI
((WdtReadback & BIT14) != 0) {(
  VOID
);

EFI_STATUS
EFIAPI
HOB list from PEI services(
  VOID
);

EFI_STATUS
EFIAPI
new WDT value based on expiration and unexpected reset(
  VOID
);

EFI_STATUS
EFIAPI
((WdtReadback & BIT24) != 0) {(
  VOID
);

EFI_STATUS
EFIAPI
updated WDT value(
  VOID
);

EFI_STATUS
EFIAPI
(WdtBase, WdtNewValue);(
  VOID
);

EFI_STATUS
EFIAPI
WDT PPIs(
  VOID
);

EFI_STATUS
EFIAPI
= (*PeiServices)->InstallPpi (PeiServices, &gPchWdtPpiGuid);(
  VOID
);

EFI_STATUS
EFIAPI
whether the WDT unexpected reset flag is set.(
  VOID
);

EFI_STATUS
EFIAPI
two reset-related PPIs:(
  VOID
);

EFI_STATUS
EFIAPI
and install PCH Reset PPI(
  VOID
);

EFI_STATUS
EFIAPI
= (PCH_RESET_PPI *)AllocatePages (EFI_SIZE_TO_PAGES (sizeof (PCH_RESET_PPI)));(
  VOID
);

EFI_STATUS
EFIAPI
second Reset PPI(
  VOID
);

EFI_STATUS
EFIAPI
= (PCH_RESET_INIT_PPI *)AllocatePages (EFI_SIZE_TO_PAGES (sizeof (PCH_RESET_INIT_PPI)));(
  VOID
);

EFI_STATUS
EFIAPI
SPI BAR0 at D31:F5, offset 0x10 (BAR0)(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT32 *)(UINTN)PchGetMmPciAddress (0, 31, 5);(
  VOID
);

EFI_STATUS
EFIAPI
MSE(
  VOID
);

EFI_STATUS
EFIAPI
and initialize SPI instance(
  VOID
);

EFI_STATUS
EFIAPI
= (PCH_SPI_INSTANCE *)AllocatePages ((
  VOID
);

EFI_STATUS
EFIAPI
PPI descriptor(
  VOID
);

EFI_STATUS
EFIAPI
1: Validate PCH SKU (must have LPC device)(
  VOID
);

EFI_STATUS
EFIAPI
(!IsPchSkuSupported ()) {(
  VOID
);

EFI_STATUS
EFIAPI
2: Ensure SBREG is programmed (D31:F0, register 0x10/0x14)(
  VOID
);

EFI_STATUS
EFIAPI
3: Program PCH cycle decoding bases(
  VOID
);

EFI_STATUS
EFIAPI
(R_PCH_ACPI_PM_BASE);(
  VOID
);

EFI_STATUS
EFIAPI
4: Validate PCH PWRM base is non-zero(
  VOID
);

EFI_STATUS
EFIAPI
(EFI_D_INFO, "PCH PWRM Base needs to be programmed before here\n");(
  VOID
);

EFI_STATUS
EFIAPI
5: Check DWR condition(
  VOID
);

EFI_STATUS
EFIAPI
= IsDwrDetected ();(
  VOID
);

EFI_STATUS
EFIAPI
6: Fabric error check and early device handling(
  VOID
);

EFI_STATUS
EFIAPI
7: Install PCH Init PreMem PPI(
  VOID
);

EFI_STATUS
EFIAPI
= PpiInstall ((EFI_PEI_PPI_DESCRIPTOR *)(UINTN)0xFFD980CC);(
  VOID
);

EFI_STATUS
EFIAPI
address(
  VOID
);

EFI_STATUS
EFIAPI
(AcpiBase == 0 || AcpiBase < 0x100) {(
  VOID
);

EFI_STATUS
EFIAPI
DMIC.SRL (DMIC locked via PCR read)(
  VOID
);

EFI_STATUS
EFIAPI
ACPI base at D31:F2 offset 0x44(
  VOID
);

EFI_STATUS
EFIAPI
0x44(
  VOID
);

EFI_STATUS
EFIAPI
enable bit(
  VOID
);

EFI_STATUS
EFIAPI
LPC device is present (D31:F0)(
  VOID
);

EFI_STATUS
EFIAPI
PWRM base from D31:F2 offset 0x48(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT32 *)(UINTN)PchGetMmPciAddress (0, 31, 2);(
  VOID
);

EFI_STATUS
EFIAPI
DMIC.SRL lock(
  VOID
);

EFI_STATUS
EFIAPI
D31:F2 for PWRM base config(
  VOID
);

EFI_STATUS
EFIAPI
PWRM base at offset 0x48(
  VOID
);

EFI_STATUS
EFIAPI
base address(
  VOID
);

EFI_STATUS
EFIAPI
DMIC.SRL(
  VOID
);

EFI_STATUS
EFIAPI
D31:F4 for TCO registers(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT32 *)(UINTN)PchGetMmPciAddress (0, 31, 4);(
  VOID
);

EFI_STATUS
EFIAPI
if TCO is already locked(
  VOID
);

EFI_STATUS
EFIAPI
(((UINT8 *)PmDevice)[0x54] & 1) {(
  VOID
);

EFI_STATUS
EFIAPI
TCO base at offset 0x54/0x55(
  VOID
);

EFI_STATUS
EFIAPI
through a table at unk_FFD980CC defining PSF(
  VOID
);

EFI_STATUS
EFIAPI
errors found, creates a HOB with error status.(
  VOID
);

EFI_STATUS
EFIAPI
(EFI_D_INFO, "PchEarlyDisabledDeviceHandling() - End\n");(
  VOID
);

EFI_STATUS
EFIAPI
13 groups of 2 GPIO pads each (groups 0x100 through 0x10C)(
  VOID
);

EFI_STATUS
EFIAPI
(GpioPad = 256; GpioPad < 269; GpioPad++) {(
  VOID
);

EFI_STATUS
EFIAPI
functions(
  VOID
);

EFI_STATUS
EFIAPI
DWR (Debug Warranty Reset) condition.(
  VOID
);

EFI_STATUS
EFIAPI
TRUE if a DWR condition is detected.(
  VOID
);

EFI_STATUS
EFIAPI
FALSE;(
  VOID
);

EFI_STATUS
EFIAPI
helpers(
  VOID
);

EFI_STATUS
EFIAPI
for completion(
  VOID
);

EFI_STATUS
EFIAPI
((*(volatile UINT32 *)(UINTN)(SbRegBase + 0) & BIT31) != 0) {(
  VOID
);

#endif /* __SIINITPREMEM_H__ */