AMI-Aptio-BIOS-Reversed/CpuMpDxe/CpuMpDxe.h at a42bdf720a4c28ee31ce9d1de96442d89ac8055c

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/** @file
  CpuMpDxe.h -- Header for CpuMpDxe

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __CPUMPDXE_H__
#define __CPUMPDXE_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
CpuMpAssertInternal(
  VOID
);

EFI_STATUS
EFIAPI
GetPcdValue(
  VOID
);

EFI_STATUS
EFIAPI
IoRead8(
  VOID
);

EFI_STATUS
EFIAPI
IoWrite8(
  VOID
);

EFI_STATUS
EFIAPI
CpuMpMicroSecondDelay(
  VOID
);

EFI_STATUS
EFIAPI
CpuMpQueryTimer(
  VOID
);

EFI_STATUS
EFIAPI
BitFieldRead32(
  VOID
);

EFI_STATUS
EFIAPI
CpuMpDebugPrint(
  VOID
);

EFI_STATUS
EFIAPI
CpuMpAssert(
  VOID
);

EFI_STATUS
EFIAPI
DetectUartBaudRate(
  VOID
);

EFI_STATUS
EFIAPI
DetectCmosPage(
  VOID
);

EFI_STATUS
EFIAPI
WaitUartReady(
  VOID
);

EFI_STATUS
EFIAPI
InitializeDriverServices(
  VOID
);

EFI_STATUS
EFIAPI
ProcessorConfigInit(
  VOID
);

EFI_STATUS
EFIAPI
SelectCpuFeatures(
  VOID
);

EFI_STATUS
EFIAPI
InitDataCollection(
  VOID
);

EFI_STATUS
EFIAPI
CpuMpDxeInit(
  VOID
);

EFI_STATUS
EFIAPI
StartAllCpus(
  VOID
);

EFI_STATUS
EFIAPI
StartCpu(
  VOID
);

EFI_STATUS
EFIAPI
SaveS3BootScript(
  VOID
);

EFI_STATUS
EFIAPI
CpuMpDxeUnload(
  VOID
);

EFI_STATUS
EFIAPI
CpuMpDxeDriverEntry(
  VOID
);

EFI_STATUS
EFIAPI
ModuleEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
UEFI table pointers(
  VOID
);

EFI_STATUS
EFIAPI
gImageHandle        = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
runtime context (allocated per-cpu config buffer)(
  VOID
);

EFI_STATUS
EFIAPI
*mCpuConfigLibConfigContextBuffer = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
System Data globals(
  VOID
);

EFI_STATUS
EFIAPI
mMpNumberOfCpus          = 0;   ///< qword_28340(
  VOID
);

EFI_STATUS
EFIAPI
*mMachineCheckAttribute   = NULL; ///< qword_282E8(
  VOID
);

EFI_STATUS
EFIAPI
performance measurement(
  VOID
);

EFI_STATUS
EFIAPI
mBootTimeTimer = 0;               ///< qword_17F58(
  VOID
);

EFI_STATUS
EFIAPI
feature bitmasks (AND-reduced across all CPUs)(
  VOID
);

EFI_STATUS
EFIAPI
mCpuFeatureEdx     = 0xFFFFFFFF;  ///< dword_18280(
  VOID
);

EFI_STATUS
EFIAPI
binding handle and processor configuration(
  VOID
);

EFI_STATUS
EFIAPI
mDriverBindingHandle  = NULL;     ///< qword_17DD0(
  VOID
);

EFI_STATUS
EFIAPI
System Data (the aggregate mMPSystemData structure)(
  VOID
);

EFI_STATUS
EFIAPI
mMPSystemData;(
  VOID
);

EFI_STATUS
EFIAPI
32 = Get64(
  VOID
);

EFI_STATUS
EFIAPI
48 = Set64(
  VOID
);

EFI_STATUS
EFIAPI
decompiled code shows 8254 PIT-based delay via IO port 0x43/0x40.(
  VOID
);

EFI_STATUS
EFIAPI
is a simplified implementation.(
  VOID
);

EFI_STATUS
EFIAPI
Start;(
  VOID
);

EFI_STATUS
EFIAPI
counter(
  VOID
);

EFI_STATUS
EFIAPI
from BaseLib: EndBit < 32, StartBit <= EndBit(
  VOID
);

EFI_STATUS
EFIAPI
(EndBit >= 32) {(
  VOID
);

EFI_STATUS
EFIAPI
CopyMemWrapper.c asserts:(
  VOID
);

EFI_STATUS
EFIAPI
((Length - 1) > ~(UINTN)Destination) {(
  VOID
);

EFI_STATUS
EFIAPI
CMOS debug level from offset 0x4B.(
  VOID
);

EFI_STATUS
EFIAPI
index 0x70 bit 7 preserves NMI; offset 0x4B = BIOS debug level.(
  VOID
);

EFI_STATUS
EFIAPI
= __inbyte (0x70);(
  VOID
);

EFI_STATUS
EFIAPI
port debug output via DebugPort protocol.(
  VOID
);

EFI_STATUS
EFIAPI
(Buffer, sizeof (Buffer), Format, Args);(
  VOID
);

EFI_STATUS
EFIAPI
via serial port (I/O 0x3F8).(
  VOID
);

EFI_STATUS
EFIAPI
(CHAR8 *Ch = Buffer; *Ch != '\0'; Ch++) {(
  VOID
);

EFI_STATUS
EFIAPI
CMOS index 0x5C for the base baud rate selector, then index 0x6C(
  VOID
);

EFI_STATUS
EFIAPI
the extended byte.(
  VOID
);

EFI_STATUS
EFIAPI
(0x72, 0x5C);(
  VOID
);

EFI_STATUS
EFIAPI
case 0xA6:  BaudRate = 57600;  break;(
  VOID
);

EFI_STATUS
EFIAPI
the actual baud rate divisor.(
  VOID
);

EFI_STATUS
EFIAPI
clock = 0x1C200 = 115200 (standard UART clock).(
  VOID
);

EFI_STATUS
EFIAPI
0x1C200 / BaudRate;(
  VOID
);

EFI_STATUS
EFIAPI
port (COM1 + 5 = 0x3FD for standard, or dynamic)(
  VOID
);

EFI_STATUS
EFIAPI
LSR until bits 5 and 6 are both set.(
  VOID
);

EFI_STATUS
EFIAPI
{(
  VOID
);

EFI_STATUS
EFIAPI
the DXE Services Table.  This is the standard library constructor(
  VOID
);

EFI_STATUS
EFIAPI
the DxeServicesTableLib performs at module startup.(
  VOID
);

EFI_STATUS
EFIAPI
= gDS->Dispatch ();(
  VOID
);

EFI_STATUS
EFIAPI
on failure.(
  VOID
);

EFI_STATUS
EFIAPI
(EFI_ERROR (Status)) {(
  VOID
);

EFI_STATUS
EFIAPI
the MM PCI Base protocol (DxeMmPciBaseLib).(
  VOID
);

EFI_STATUS
EFIAPI
provides the MmPciBase (mPciUsra) for memory-mapped PCI config access.(
  VOID
);

EFI_STATUS
EFIAPI
(mPciUsra == NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
from CpRcPkg(
  VOID
);

EFI_STATUS
EFIAPI
per-CPU context blocks (zero-initialized from allocation).(
  VOID
);

EFI_STATUS
EFIAPI
C code also initializes lists at unk_17C80 and unk_17D00.(
  VOID
);

EFI_STATUS
EFIAPI
(Index = 0; Index < NumberOfCpus; Index++) {(
  VOID
);

EFI_STATUS
EFIAPI
a 4KB config buffer (one physical page) for processor config I/O.(
  VOID
);

EFI_STATUS
EFIAPI
is used for communicating configuration data between BSP and APs.(
  VOID
);

EFI_STATUS
EFIAPI
= 0xFFFFFFFFFFFFFFFFULL;(
  VOID
);

EFI_STATUS
EFIAPI
page = 4KB(
  VOID
);

EFI_STATUS
EFIAPI
the config buffer header.(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT64 *)(UINTN)ConfigPagesAddress;(
  VOID
);

EFI_STATUS
EFIAPI
size (32K)(
  VOID
);

EFI_STATUS
EFIAPI
CPUs in the config buffer.(
  VOID
);

EFI_STATUS
EFIAPI
original code writes 1 to the marker dword.(
  VOID
);

EFI_STATUS
EFIAPI
(BufferIndex = 0; BufferIndex < NumberOfCpus; BufferIndex++) {(
  VOID
);

EFI_STATUS
EFIAPI
per-CPU data array (1088 bytes each) - qword_28350(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT64 *)CpuMpAllocatePool ((UINTN)(1088 * NumberOfCpus));(
  VOID
);

EFI_STATUS
EFIAPI
linked list heads (16 bytes each) - qword_28358(
  VOID
);

EFI_STATUS
EFIAPI
each as an empty doubly-linked list.(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT64 *)CpuMpAllocatePool ((UINTN)(16 * NumberOfCpus));(
  VOID
);

EFI_STATUS
EFIAPI
per-CPU flags array (32 bytes each) - qword_28368(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT64)CpuMpAllocatePool ((UINTN)(32 * NumberOfCpus));(
  VOID
);

EFI_STATUS
EFIAPI
per-CPU flags shadow array (32 bytes each) - qword_28360(
  VOID
);

EFI_STATUS
EFIAPI
index array: initialize with sequential indices - qword_28370(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT64)CpuMpAllocatePool ((UINTN)(24 * NumberOfCpus));(
  VOID
);

EFI_STATUS
EFIAPI
CPU count to CpuConfigLib via PCD 151.(
  VOID
);

EFI_STATUS
EFIAPI
connects the config context to the library's internal tracking.(
  VOID
);

EFI_STATUS
EFIAPI
= SetPcdValue (151, NumberOfCpus);(
  VOID
);

EFI_STATUS
EFIAPI
per-CPU feature arrays(
  VOID
);

EFI_STATUS
EFIAPI
= 128 bytes per CPU (qword_282E8)(
  VOID
);

EFI_STATUS
EFIAPI
UINT64 per CPU(
  VOID
);

EFI_STATUS
EFIAPI
= 1 byte per CPU (qword_282B8)(
  VOID
);

EFI_STATUS
EFIAPI
= 8 bytes per CPU (qword_18260)(
  VOID
);

EFI_STATUS
EFIAPI
= 24 bytes per CPU (qword_28300)(
  VOID
);

EFI_STATUS
EFIAPI
= 1 byte per CPU (qword_282F0)(
  VOID
);

EFI_STATUS
EFIAPI
= 8 bytes per CPU (qword_282F8)(
  VOID
);

EFI_STATUS
EFIAPI
the global config context buffer pointer for CpuConfigLib.(
  VOID
);

EFI_STATUS
EFIAPI
pointer is stored in qword_17FC8 and is used by multiple library functions.(
  VOID
);

EFI_STATUS
EFIAPI
= (VOID *)mMpCpuList;(
  VOID
);

EFI_STATUS
EFIAPI
PCD 155 for platform type and store it.(
  VOID
);

EFI_STATUS
EFIAPI
feature masks to all-ones (all features assumed present(
  VOID
);

EFI_STATUS
EFIAPI
a CPU clears a bit).(
  VOID
);

EFI_STATUS
EFIAPI
= 0xFFFFFFFF;(
  VOID
);

EFI_STATUS
EFIAPI
CPUID leaf 0x1 from CpuConfigLib.(
  VOID
);

EFI_STATUS
EFIAPI
= (CPUID_REGISTERS *)CpuConfigLibGetCpuid ((
  VOID
);

EFI_STATUS
EFIAPI
CPUID leaf 0x80000001 for extended features.(
  VOID
);

EFI_STATUS
EFIAPI
&= CpuidRegisters->Edx;(
  VOID
);

EFI_STATUS
EFIAPI
PCD 146 (CPU data collection enable flag) and set bit 1.(
  VOID
);

EFI_STATUS
EFIAPI
PCD 147 for a specific feature enable flag (bit 1).(
  VOID
);

EFI_STATUS
EFIAPI
the feature in PCD 145.(
  VOID
);

EFI_STATUS
EFIAPI
= GetPcdValue (145);(
  VOID
);

EFI_STATUS
EFIAPI
1: Read platform type from CpuConfigLib (PCD 155).(
  VOID
);

EFI_STATUS
EFIAPI
determines which feature set to enable.(
  VOID
);

EFI_STATUS
EFIAPI
= GetPcdValue (155);(
  VOID
);

EFI_STATUS
EFIAPI
2: Initialize data collection subsystem.(
  VOID
);

EFI_STATUS
EFIAPI
();(
  VOID
);

EFI_STATUS
EFIAPI
3: Initialize per-CPU feature subsystems.(
  VOID
);

EFI_STATUS
EFIAPI
correspond to the source files in the CpuMpDxe directory.(
  VOID
);

EFI_STATUS
EFIAPI
4: Allocate processor configuration structure (104 bytes).(
  VOID
);

EFI_STATUS
EFIAPI
= (PROCESSOR_CONFIG_DATA *)CpuMpAllocatePool (sizeof (PROCESSOR_CONFIG_DATA));(
  VOID
);

EFI_STATUS
EFIAPI
in processor configuration structure.(
  VOID
);

EFI_STATUS
EFIAPI
the config buffer from the pages allocated during ProcessorConfigInit.(
  VOID
);

EFI_STATUS
EFIAPI
base is stored at qword_18268 + 8.(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT64 *)(UINTN)1;  // Placeholder: real address set in ProcessorConfigInit(
  VOID
);

EFI_STATUS
EFIAPI
configuration to CpuConfigLib via PCD 156.(
  VOID
);

EFI_STATUS
EFIAPI
= SetPcdValue (156, (UINT64)mProcessorConfig);(
  VOID
);

EFI_STATUS
EFIAPI
5: Install the MP Services protocol or other protocols.(
  VOID
);

EFI_STATUS
EFIAPI
decompile shows InstallMultipleProtocolInterfaces with GUID at 0x186A0.(
  VOID
);

EFI_STATUS
EFIAPI
= mDriverBindingHandle;(
  VOID
);

EFI_STATUS
EFIAPI
with actual GUID at 0x186A0(
  VOID
);

EFI_STATUS
EFIAPI
6: Register for callback on a specific protocol notification.(
  VOID
);

EFI_STATUS
EFIAPI
original calls sub_F7A0 with unk_17790 as the protocol GUID and(
  VOID
);

EFI_STATUS
EFIAPI
as the notification function.(
  VOID
);

EFI_STATUS
EFIAPI
CMOS page and baud rate (serial init).(
  VOID
);

EFI_STATUS
EFIAPI
UART divisor.(
  VOID
);

EFI_STATUS
EFIAPI
= IoRead8 ((UINT16)(CmosPage + 3));(
  VOID
);

EFI_STATUS
EFIAPI
DLAB, set FIFO.(
  VOID
);

EFI_STATUS
EFIAPI
((UINT16)(CmosPage + 2), 0);(
  VOID
);

EFI_STATUS
EFIAPI
for the speedstep flag from sub_780().(
  VOID
);

EFI_STATUS
EFIAPI
and validate the RTC timer.(
  VOID
);

EFI_STATUS
EFIAPI
//(
  VOID
);

EFI_STATUS
EFIAPI
for the timeout window.(
  VOID
);

EFI_STATUS
EFIAPI
original uses a 357-CPU-index-based timeout comparison.(
  VOID
);

EFI_STATUS
EFIAPI
loop with timeout check(
  VOID
);

EFI_STATUS
EFIAPI
speedstep-specific delay compensation.(
  VOID
);

EFI_STATUS
EFIAPI
divisor to 1(
  VOID
);

EFI_STATUS
EFIAPI
each AP.(
  VOID
);

EFI_STATUS
EFIAPI
(CpuIndex = 0; CpuIndex < (UINTN)mMpNumberOfCpus; CpuIndex++) {(
  VOID
);

EFI_STATUS
EFIAPI
BSP(
  VOID
);

EFI_STATUS
EFIAPI
the APIC ID for this processor.(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT32)GetPcdValue (ProcessorNumber);  // Placeholder: read from CPU map(
  VOID
);

EFI_STATUS
EFIAPI
INIT IPI.(
  VOID
);

EFI_STATUS
EFIAPI
(0x8B, 0);                             // Clear ICR(
  VOID
);

EFI_STATUS
EFIAPI
IPI (fixed, edge, assert)(
  VOID
);

EFI_STATUS
EFIAPI
delay (10ms per spec).(
  VOID
);

EFI_STATUS
EFIAPI
(10000);(
  VOID
);

EFI_STATUS
EFIAPI
first SIPI.(
  VOID
);

EFI_STATUS
EFIAPI
= 0x10000 >> 12;                   // Reset vector page(
  VOID
);

EFI_STATUS
EFIAPI
delay (200us per spec).(
  VOID
);

EFI_STATUS
EFIAPI
(200);(
  VOID
);

EFI_STATUS
EFIAPI
second SIPI.(
  VOID
);

EFI_STATUS
EFIAPI
(0x8B, (ApicId << 32) | 0x600 | StartupAddress);(
  VOID
);

EFI_STATUS
EFIAPI
for AP to report in.(
  VOID
);

EFI_STATUS
EFIAPI
(100);(
  VOID
);

EFI_STATUS
EFIAPI
the S3 boot script protocol.(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->LocateProtocol ((
  VOID
);

EFI_STATUS
EFIAPI
IO write boot script entries for each MSR programmed during init.(
  VOID
);

EFI_STATUS
EFIAPI
EFI_SUCCESS;(
  VOID
);

EFI_STATUS
EFIAPI
globals.(
  VOID
);

EFI_STATUS
EFIAPI
= ImageHandle;(
  VOID
);

EFI_STATUS
EFIAPI
DXE services and locate MM PCI base protocol.(
  VOID
);

EFI_STATUS
EFIAPI
HII protocols.(
  VOID
);

EFI_STATUS
EFIAPI
and configure the serial port baud rate and CMOS wait state.(
  VOID
);

EFI_STATUS
EFIAPI
if the UART is already configured for this baud rate.(
  VOID
);

EFI_STATUS
EFIAPI
the divisor doesn't match, reprogram it.(
  VOID
);

EFI_STATUS
EFIAPI
(CurrentDivisor != (UINT16)Divisor) {(
  VOID
);

EFI_STATUS
EFIAPI
for CPU 0 stepping/workaround via CMOS page.(
  VOID
);

EFI_STATUS
EFIAPI
PCD 1024068 (byte) and PCD 1024064 (base address) to check(
  VOID
);

EFI_STATUS
EFIAPI
specific CPU stepping workaround.(
  VOID
);

EFI_STATUS
EFIAPI
the byte at PCD 1024068 is >= 0 (signed), then perform a workaround(
  VOID
);

EFI_STATUS
EFIAPI
setting bit 7 of the byte at PCD 1024064 + 1280.(
  VOID
);

EFI_STATUS
EFIAPI
Stepping;(
  VOID
);

EFI_STATUS
EFIAPI
CPU count from PCD 151.(
  VOID
);

EFI_STATUS
EFIAPI
= GetPcdValue (151);(
  VOID
);

EFI_STATUS
EFIAPI
and initialize MP system data structures.(
  VOID
);

EFI_STATUS
EFIAPI
= ProcessorConfigInit (NumberOfCpus);(
  VOID
);

EFI_STATUS
EFIAPI
the boot TSC.(
  VOID
);

EFI_STATUS
EFIAPI
speedstep flag.(
  VOID
);

EFI_STATUS
EFIAPI
= IoRead8 (0x780);        // Simplified: actual call to sub_780()(
  VOID
);

EFI_STATUS
EFIAPI
TSC for timing(
  VOID
);

EFI_STATUS
EFIAPI
timeout-adjusted delay loop using PCD 1288.(
  VOID
);

EFI_STATUS
EFIAPI
with timeout using the CPU index-based check.(
  VOID
);

EFI_STATUS
EFIAPI
= GetPcdValue (1288);(
  VOID
);

EFI_STATUS
EFIAPI
original algorithm compares timer values with a wraparound(
  VOID
);

EFI_STATUS
EFIAPI
(((TimerStart + 357 - NewTimer) & 0x800000) != 0) {(
  VOID
);

EFI_STATUS
EFIAPI
the final timer measurement.(
  VOID
);

EFI_STATUS
EFIAPI
workaround: restore UART speed.(
  VOID
);

EFI_STATUS
EFIAPI
+ 1 = IER(
  VOID
);

EFI_STATUS
EFIAPI
+ 0 = DLL(
  VOID
);

EFI_STATUS
EFIAPI
DLAB + LCR(
  VOID
);

EFI_STATUS
EFIAPI
+ 3 = LCR(
  VOID
);

EFI_STATUS
EFIAPI
path: no speedstep compensation needed.(
  VOID
);

EFI_STATUS
EFIAPI
the main initialization dispatcher.(
  VOID
);

EFI_STATUS
EFIAPI
= CpuMpDxeInit ();(
  VOID
);

#endif /* __CPUMPDXE_H__ */