OemPlatformDxePhase

Function Table

Address	Name
	ReadUnaligned64
	CompareGuid
	DebugPrint
	DebugAssert
	InternalGetDxeServicesTable
	OemPlatformCheckAndLogDimms
	OemPlatformDxePhaseInitialize
	ModuleEntryPoint
Global	Data
They	follow the UEFI standard library pattern for boot services table libs.
Addresses	in comments reference the .data section in the original PE image.
Static	buffers used by CopyMem (internal)
static	char DstBuffer[0x48]; // @ 0x1500: destination buffer (72 bytes)
Helper	Functions
Overlapping	with Dst after Src: copy backwards
CopyMemBackwards	(Dst, Src, Count);
CountAligned	= Count >> 3;
Validate	that (Count - 1) does not overflow the address space
for	either destination or source.
if	((Count - 1) > (UINT64)(-1) - (UINT64)Dst) {
Debug	Output Functions
Allocation	too small or failed - skip protocol lookup
return	NULL;
Read	the debug level from CMOS register 0x4B
CmosValue	= __inbyte (CMOS_INDEX_PORT);
Decode	CMOS debug level
if	(CmosDebugLevel > 3) {
EFI_D_ERROR	} else {
EFI_D_WARN	}
If	the message ErrorLevel matches the filter, forward to protocol
if	((FilterMask & ErrorLevel) != 0) {
Configuration	Table and HOB Services
Each	configuration table entry is 24 bytes:
Advance	to next HOB using the length field
HobStart	*= (UINT16 )((UINT8* )HobStart + HobLength);**
PCD	Protocol Services
IPMI	SEL Logging for Disabled DIMMs
Build	the SEL record command frame
Locate	the memory topology HOB
CurrentHob	*= (UINT16 )GetHobList ();**
Memory	topology data starts at offset +5346 from the HOB structure
SocketTopology	*= (UINT8 )CurrentHob + MEM_HOB_BASE_OFFSET;**
Iterate	over 10 sockets
for	(Socket = 0; Socket < MAX_SOCKETS; Socket++) {
6	channels per socket
for	(Channel = 0; Channel < MAX_CHANNELS; Channel++) {
2	DIMMs per channel
for	(Dimm = 0; Dimm < MAX_DIMMS; Dimm++) {
DIMM	is present - check if enabled
if	(DimmEntry[1] == 0) {
DIMM	is disabled - log via IPMI SEL
DebugPrint	(
Build	SEL record for the disabled DIMM
OEM	System Event Record
Encode	channel position:
Top	nibble = Channel, bottom nibble = DimmIndex
Clear	remaining event data
Send	IPMI Add SEL Entry
if	**(gIpmiTransport != NULL	**
IPMI	Add SEL command via transport protocol
Status	*= ((IPMI_TRANSPORT_PROTOCOL )gIpmiTransport)->AddSel (**
SEL	entry type
Reserved	IPMI_NETFN_STORAGE
Main	Entry Point - Module Initialization
Phase	1: Cache UEFI Boot Services pointers
gImageHandle	= ImageHandle;
Phase	2: Initialize DXE Services Table (for GCD access)
Status	= InternalGetDxeServicesTable (&gEfiDxeServicesTableGuid, &gDxeServicesTable);
Phase	3: Locate and cache MM PCI Base Protocol
if	(gMmPciUsra == NULL) {
Phase	4: Initialize HOB list for memory topology
GetHobList	();
Phase	5: Get PCD protocol and configure PCIe segment bus table size
PcdProtocol	= GetPcdProtocol ();
PCD	protocol vtable interface:
Phase	6: Initialize PCIe segment bus table (CopyMem)
CopyMem	*(&DstBuffer, (void )PcieSegBusTableSize, PcieSegBusTableSize);**
Phase	7: Check memory topology and log disabled DIMMs
Module	Entry Point (AutoGen)
Initialize	platform (boot services, DXE table, PCIe, PCD, etc.)
OemPlatformDxePhaseInitialize	(ImageHandle, SystemTable);
Log	disabled DIMMs to IPMI SEL
Write	completion checkpoint to CMOS
0x72	= 0x71 (CMOS index register for extended RAM)
0x73	= 0xBB (CMOS data register - platform init complete)
__outbyte	(0x72, 0x71);

Generated by HR650X BIOS Decompilation Project