OpromUpdateDxeLightningRidgeEXRP

Function Table

Address	Name	Description
	ReadUnaligned64
	HobCompareGuid
	UbaDebugPrint
	UbaAssertPrint
	GetUbaConfigBoardInfo
	GetUbaConfigSlotCount
	GetUbaConfigSlotData
	SetPcieSlotNumber
	SetPcieSlotNumberInit
	OpromUpdateDxeLightningRidgeEXRP
UBA	Protocol GUID: E03E0D46-5263-4845-B0A4-58D57B3177E2
extern	EFI_GUID gUbaProtocolGuid;
PCI	Root Bridge IO Protocol GUID: 2F707EBB-4A1A-11D4-9A38-0090273FC14D
extern	EFI_GUID gEfiPciRootBridgeIoProtocolGuid;
HOB	List GUID: 7739F24C-93D7-11D4-9A3A-0090273FC14D
extern	EFI_GUID gEfiHobListGuid;
UBA	Config Board Protocol GUID: 36232936-0E76-31C8-A13A-3AF2FC1C3932
Used	for board-specific configuration retrieval
extern	EFI_GUID gUbaConfigBoardProtocolGuid;
Lightning	Ridge EXRP SKU GUID: 371BD79C-DE79-4C5F-AA2B-BC9EBEFA988F
extern	EFI_GUID gLightningRidgeExrpSkuGuid;
Globals	//
Read	board type from CMOS index 0x4B
CmosData	= IoRead8 (0x70);
BoardType	**= (MmioRead8 (0xFDAF0490) & 2)	1;**
SlotCfg	points into the slot table at 0xED1.
Each	entry is 4 bytes: {SlotNum, Flags, Bus, DevFn}
The	-1 offset reads the previous entry's slot number byte.
SlotCfg	*= (UINT8 )&mUbaSlotNumberCfg;**
Bus	from previous entry
Device	number
Construct	PCI config address:
AddrBase	**= ((Bus	((Device	(Fn << 8)) << 8)) << 8)**
Then	read PCI config registers at offset 0x19 and 0x1A
to	get slot base/limit for this bus/dev/fn.
AddrBase	**= (UINT64)((Bus	((Device	(Fn << 8)) << 8)) << 8);**
Advance	4 bytes per entry (was 3 in original, corrected)

Generated by HR650X BIOS Decompilation Project