/** @file
  POSTDataTransfer.h -- Header for POSTDataTransfer

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __POSTDATATRANSFER_H__
#define __POSTDATATRANSFER_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
GetDebugInterface(
  VOID
);

EFI_STATUS
EFIAPI
DebugPrint(
  VOID
);

EFI_STATUS
EFIAPI
DebugAssert(
  VOID
);

EFI_STATUS
EFIAPI
UnalignedRead64(
  VOID
);

EFI_STATUS
EFIAPI
GuidCompare(
  VOID
);

EFI_STATUS
EFIAPI
HobLocate(
  VOID
);

EFI_STATUS
EFIAPI
MmioPciExpressRead32(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressBaseAddr(
  VOID
);

EFI_STATUS
EFIAPI
PcdLocate(
  VOID
);

EFI_STATUS
EFIAPI
ProcessPci(
  VOID
);

EFI_STATUS
EFIAPI
ProcessSADTAD(
  VOID
);

EFI_STATUS
EFIAPI
CollectPOSTData(
  VOID
);

EFI_STATUS
EFIAPI
ModuleEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
variables(
  VOID
);

EFI_STATUS
EFIAPI
gImageHandle;(
  VOID
);

EFI_STATUS
EFIAPI
UINT64             gIioUdsProtocol;               // qword_2710(
  VOID
);

EFI_STATUS
EFIAPI
UINT64             gMtrrSettings;                 // qword_2748(
  VOID
);

EFI_STATUS
EFIAPI
UINT64             gPort80DebugValue;             // qword_2758(
  VOID
);

EFI_STATUS
EFIAPI
definitions (from UEFI spec / platform headers)(
  VOID
);

EFI_STATUS
EFIAPI
gEfiPciRootBridgeIoProtocolGuid = { 0x2F707EBB, 0x4A1A, 0x11D4, { 0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } };(
  VOID
);

EFI_STATUS
EFIAPI
entry: { Bus, Device, Function, Register offset, Value mask }(
  VOID
);

EFI_STATUS
EFIAPI
entries (0x2B8 bytes), 5 bytes each(
  VOID
);

EFI_STATUS
EFIAPI
CONST UINT8  mSadAdTopologyTable[696 * 5] = { 0 };(
  VOID
);

EFI_STATUS
EFIAPI
if we have enough buffer space (>= 16 bytes)(
  VOID
);

EFI_STATUS
EFIAPI
(gBS >= 0x10) {(
  VOID
);

EFI_STATUS
EFIAPI
not found: ASSERT and fall through(
  VOID
);

EFI_STATUS
EFIAPI
(0x80000000, "\nASSERT_EFI_ERROR (Status = %r)\n", 0x800000000000000E);(
  VOID
);

EFI_STATUS
EFIAPI
that the address fits within PCIe config space range(
  VOID
);

EFI_STATUS
EFIAPI
((Address & ~0xFFFFFFF) != 0) {(
  VOID
);

EFI_STATUS
EFIAPI
all handles that support gEfiPciRootBridgeIoProtocolGuid(
  VOID
);

EFI_STATUS
EFIAPI
= 0;(
  VOID
);

EFI_STATUS
EFIAPI
over all PCI root bridge handles(
  VOID
);

EFI_STATUS
EFIAPI
(HandleIndex = 0; HandleIndex < NumHandles; HandleIndex++) {(
  VOID
);

EFI_STATUS
EFIAPI
the PCI Root Bridge IO protocol for this handle(
  VOID
);

EFI_STATUS
EFIAPI
= NULL;(
  VOID
);

EFI_STATUS
EFIAPI
resource list to determine bus range(
  VOID
);

EFI_STATUS
EFIAPI
= (*(UINT64 (__fastcall **)(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *, UINT64 *))((
  VOID
);

EFI_STATUS
EFIAPI
no resource list, do a full bus scan (0-255)(
  VOID
);

EFI_STATUS
EFIAPI
(ResourceList == 0) {(
  VOID
);

EFI_STATUS
EFIAPI
initial bus range from resource list(
  VOID
);

EFI_STATUS
EFIAPI
= StartBus;(
  VOID
);

EFI_STATUS
EFIAPI
all buses, devices, functions(
  VOID
);

EFI_STATUS
EFIAPI
(Bus <= EndBus) {(
  VOID
);

EFI_STATUS
EFIAPI
up to 8 times on failure(
  VOID
);

EFI_STATUS
EFIAPI
= PciRootBridgeIo->Pci.Read ((
  VOID
);

EFI_STATUS
EFIAPI
if device is present (VendorId != 0xFFFF)(
  VOID
);

EFI_STATUS
EFIAPI
(VendorId == 0xFFFF) {(
  VOID
);

EFI_STATUS
EFIAPI
PCI header type(
  VOID
);

EFI_STATUS
EFIAPI
full config space (64 bytes)(
  VOID
);

EFI_STATUS
EFIAPI
= PCI_EXPRESS_ADDRESS (Bus, Function, Device, 0);(
  VOID
);

EFI_STATUS
EFIAPI
PCI device (non-multifunction or function 0)(
  VOID
);

EFI_STATUS
EFIAPI
= ConfigSpace[0x11];  // Subsystem Vendor ID (or similar)(
  VOID
);

EFI_STATUS
EFIAPI
(0x80000000, "[%X/%X/%X]  ", Bus, Device, Function);(
  VOID
);

EFI_STATUS
EFIAPI
((ConfigSpace[BarIndex * 4] & 2) != 0 ||(
  VOID
);

EFI_STATUS
EFIAPI
= *(UINT32 *)&ConfigSpace[BarIndex * 4];(
  VOID
);

EFI_STATUS
EFIAPI
register backup(
  VOID
);

EFI_STATUS
EFIAPI
decoding by clearing command register bits(
  VOID
);

EFI_STATUS
EFIAPI
PCI config space offset for the BAR(
  VOID
);

EFI_STATUS
EFIAPI
(IpmiDataReady) {(
  VOID
);

EFI_STATUS
EFIAPI
= ~0ULL;(
  VOID
);

EFI_STATUS
EFIAPI
command register(
  VOID
);

EFI_STATUS
EFIAPI
via IPMI(
  VOID
);

EFI_STATUS
EFIAPI
= 4865;(
  VOID
);

EFI_STATUS
EFIAPI
multi-function devices(
  VOID
);

EFI_STATUS
EFIAPI
resource list to find acpi (0x79) and pnp (0x02) descriptors(
  VOID
);

EFI_STATUS
EFIAPI
(ResourceList != 0) {(
  VOID
);

EFI_STATUS
EFIAPI
tag(
  VOID
);

EFI_STATUS
EFIAPI
= 1;(
  VOID
);

EFI_STATUS
EFIAPI
2 descriptor (DWORD address space): extract bus range(
  VOID
);

EFI_STATUS
EFIAPI
= *(UINT16 *)(ResourceList + 14);(
  VOID
);

EFI_STATUS
EFIAPI
the handle buffer(
  VOID
);

EFI_STATUS
EFIAPI
(HandleBuffer != NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
gEfiIioUdsProtocolGuid(
  VOID
);

EFI_STATUS
EFIAPI
= (*(UINT64 (__fastcall **)(VOID *, UINT64, UINT64 *))(gBootServices + 320))((
  VOID
);

EFI_STATUS
EFIAPI
gEfiCpuCsrAccessGuid(
  VOID
);

EFI_STATUS
EFIAPI
over 4 possible sockets(
  VOID
);

EFI_STATUS
EFIAPI
(Socket = 0; Socket < 4; Socket++) {(
  VOID
);

EFI_STATUS
EFIAPI
is present(
  VOID
);

EFI_STATUS
EFIAPI
SAD/AD topology table (696 entries)(
  VOID
);

EFI_STATUS
EFIAPI
= 9 * Socket;(
  VOID
);

EFI_STATUS
EFIAPI
pass: read CPUBUSNO and CPUBUSNO1 for this socket(
  VOID
);

EFI_STATUS
EFIAPI
= (*(UINT32 (__fastcall **)(UINT8, UINT32, UINT32))(gGpioCsrAccessProtocol + 8))((
  VOID
);

EFI_STATUS
EFIAPI
CSR(
  VOID
);

EFI_STATUS
EFIAPI
CPUBUSNO_VALID(
  VOID
);

EFI_STATUS
EFIAPI
information valid: store it(
  VOID
);

EFI_STATUS
EFIAPI
bus information for this socket; use default(
  VOID
);

EFI_STATUS
EFIAPI
(0x80000000, "No Bus Information in Socket %x.", Socket);(
  VOID
);

EFI_STATUS
EFIAPI
the full PCI address using the socket's bus number(
  VOID
);

EFI_STATUS
EFIAPI
= gSocketBusInfo[Socket][1 + SadAdEntry[4]];(
  VOID
);

EFI_STATUS
EFIAPI
process CSR-based DIMM/DDRIO data for the 24 VCU/MC channels(
  VOID
);

EFI_STATUS
EFIAPI
(Index = 0; Index < 24; Index++) {(
  VOID
);

EFI_STATUS
EFIAPI
selector register(
  VOID
);

EFI_STATUS
EFIAPI
CSR selector(
  VOID
);

EFI_STATUS
EFIAPI
the data register(
  VOID
);

EFI_STATUS
EFIAPI
= (*(UINT32 (__fastcall **)(UINT8, UINT8, UINT32))(gGpioCsrAccessProtocol + 40))((
  VOID
);

EFI_STATUS
EFIAPI
the boot services timer event(
  VOID
);

EFI_STATUS
EFIAPI
IPMI transport protocol is available(
  VOID
);

EFI_STATUS
EFIAPI
(gIpmiTransport == 0) {(
  VOID
);

EFI_STATUS
EFIAPI
PCI data and SAD/AD data(
  VOID
);

EFI_STATUS
EFIAPI
();(
  VOID
);

EFI_STATUS
EFIAPI
global variables (BootServices, SystemTable, etc.)(
  VOID
);

EFI_STATUS
EFIAPI
(ImageHandle, SystemTable);(
  VOID
);

EFI_STATUS
EFIAPI
a timer event to collect POST data(
  VOID
);

EFI_STATUS
EFIAPI
= (*(EFI_STATUS (__fastcall **)(UINT64, UINT64, EFI_EVENT *))(gBootServices + 80))((
  VOID
);

EFI_STATUS
EFIAPI
16,            // NotifyTpl(
  VOID
);

#endif /* __POSTDATATRANSFER_H__ */