/** @file
  PcatSingleSegmentPciCfg2Pei.h -- Header for PcatSingleSegmentPciCfg2Pei

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __PCATSINGLESEGMENTPCICFG2PEI_H__
#define __PCATSINGLESEGMENTPCICFG2PEI_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
PciCfg2Read(
  VOID
);

EFI_STATUS
EFIAPI
PciCfg2Write(
  VOID
);

EFI_STATUS
EFIAPI
PciCfg2Modify(
  VOID
);

EFI_STATUS
EFIAPI
ModuleEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressAddressToOffset(
  VOID
);

EFI_STATUS
EFIAPI
ReadIdtr(
  VOID
);

EFI_STATUS
EFIAPI
GetPciExpressBaseAddr(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressRead8(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressWrite8(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressRead16(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressWrite16(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressRead32(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressWrite32(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressOr8(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressOr16(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressOr32(
  VOID
);

EFI_STATUS
EFIAPI
UnalignedRead16(
  VOID
);

EFI_STATUS
EFIAPI
UnalignedWrite16(
  VOID
);

EFI_STATUS
EFIAPI
UnalignedRead32(
  VOID
);

EFI_STATUS
EFIAPI
UnalignedWrite32(
  VOID
);

EFI_STATUS
EFIAPI
AlignedRead16(
  VOID
);

EFI_STATUS
EFIAPI
AlignedWrite16(
  VOID
);

EFI_STATUS
EFIAPI
GetPlatformErrorStatus(
  VOID
);

EFI_STATUS
EFIAPI
ReportAssert(
  VOID
);

EFI_STATUS
EFIAPI
ReportDebugMsg(
  VOID
);

EFI_STATUS
EFIAPI
for PCD database PPI lookup(
  VOID
);

EFI_STATUS
EFIAPI
GUID: {057A449A-1FDC-4C06-BFC9-F53F6A99BB92}(
  VOID
);

EFI_STATUS
EFIAPI
- EFI_PEI_PCI_CFG2_PPI instance(
  VOID
);

EFI_STATUS
EFIAPI
EFI_PEI_PCI_CFG2_PPI mPrivateData;(
  VOID
);

EFI_STATUS
EFIAPI
Descriptor(
  VOID
);

EFI_STATUS
EFIAPI
EFI_PEI_PPI_DESCRIPTOR mPpiDescriptor = {(
  VOID
);

EFI_STATUS
EFIAPI
declarations(
  VOID
);

EFI_STATUS
EFIAPI
entry point(
  VOID
);

EFI_STATUS
EFIAPI
PRIVATE_DATA address in SystemTable reserved slot.(
  VOID
);

EFI_STATUS
EFIAPI
effectively associates the private data with ImageHandle.(
  VOID
);

EFI_STATUS
EFIAPI
to: ImageHandle->SystemTable->Something = &mPrivateData(
  VOID
);

EFI_STATUS
EFIAPI
PEI Services Table pointer(
  VOID
);

EFI_STATUS
EFIAPI
= GetPeiServicesTablePtr();(
  VOID
);

EFI_STATUS
EFIAPI
EFI_PEI_PCI_CFG2_PPI(
  VOID
);

EFI_STATUS
EFIAPI
= (*PeiServices)->InstallPpi (PeiServices, &mPpiDescriptor);(
  VOID
);

EFI_STATUS
EFIAPI
on failure(
  VOID
);

EFI_STATUS
EFIAPI
(EFI_ERROR (Status)) {(
  VOID
);

EFI_STATUS
EFIAPI
Express address to MMIO offset conversion(
  VOID
);

EFI_STATUS
EFIAPI
EFI_PEI_PCI_CFG2_PPI Address format packs:(
  VOID
);

EFI_STATUS
EFIAPI
0: Register (bits 7:0) - config register offset(
  VOID
);

EFI_STATUS
EFIAPI
1: Function (bits 2:0)(
  VOID
);

EFI_STATUS
EFIAPI
2: Device (bits 4:0)(
  VOID
);

EFI_STATUS
EFIAPI
3: Bus (bits 7:0)(
  VOID
);

EFI_STATUS
EFIAPI
4-7: ExtendedRegister (32-bit, if non-zero overrides Register)(
  VOID
);

EFI_STATUS
EFIAPI
MMIO offset = (Bus * 32 + Device) * 8 + Function) * 4096 + Register(
  VOID
);

EFI_STATUS
EFIAPI
<< 20 | Device << 15 | Function << 12 | Register(
  VOID
);

EFI_STATUS
EFIAPI
EFIAPI(
  VOID
);

EFI_STATUS
EFIAPI
config space access (>= 256 bytes offset, for ECAM)(
  VOID
);

EFI_STATUS
EFIAPI
(ExtendedRegister & 0xFFF)(
  VOID
);

EFI_STATUS
EFIAPI
config space access (< 256 bytes offset)(
  VOID
);

EFI_STATUS
EFIAPI
= PciAddress[1] & 7;(
  VOID
);

EFI_STATUS
EFIAPI
CFG2 Read(
  VOID
);

EFI_STATUS
EFIAPI
from PCI configuration space at the given Address.(
  VOID
);

EFI_STATUS
EFIAPI
UINT8 (0), UINT16 (1), UINT32 (2), and UINT64 (3) widths.(
  VOID
);

EFI_STATUS
EFIAPI
misaligned accesses by breaking into byte/word reads as needed.(
  VOID
);

EFI_STATUS
EFIAPI
(Buffer, PciExpressRead16 (Offset));(
  VOID
);

EFI_STATUS
EFIAPI
(Buffer, PciExpressRead32 (Offset));(
  VOID
);

EFI_STATUS
EFIAPI
CFG2 Write(
  VOID
);

EFI_STATUS
EFIAPI
to PCI configuration space at the given Address.(
  VOID
);

EFI_STATUS
EFIAPI
(Offset, ((UINT8 *)Buffer)[0]);(
  VOID
);

EFI_STATUS
EFIAPI
(Offset, UnalignedRead16 (Buffer));(
  VOID
);

EFI_STATUS
EFIAPI
(Offset, UnalignedRead32 (Buffer));(
  VOID
);

EFI_STATUS
EFIAPI
CFG2 Modify (Read-Modify-Write)(
  VOID
);

EFI_STATUS
EFIAPI
a read-modify-write on PCI configuration space.(
  VOID
);

EFI_STATUS
EFIAPI
= (old_value & ~ClearBits) | SetBits(
  VOID
);

EFI_STATUS
EFIAPI
(Offset, ~((UINT8 *)ClearBits)[0], ((UINT8 *)SetBits)[0]);(
  VOID
);

EFI_STATUS
EFIAPI
(Offset, ~UnalignedRead16 (ClearBits), UnalignedRead16 (SetBits));(
  VOID
);

EFI_STATUS
EFIAPI
(Offset, ~UnalignedRead32 (ClearBits), UnalignedRead32 (SetBits));(
  VOID
);

EFI_STATUS
EFIAPI
utility functions (library wrappers)(
  VOID
);

EFI_STATUS
EFIAPI
source < destination and ranges overlap (backward copy case):(
  VOID
);

EFI_STATUS
EFIAPI
copy from end(
  VOID
);

EFI_STATUS
EFIAPI
((UINTN)Source < (UINTN)Destination &&(
  VOID
);

EFI_STATUS
EFIAPI
backwards from the end, one byte at a time(
  VOID
);

EFI_STATUS
EFIAPI
memmove (Destination, Source, Size);(
  VOID
);

EFI_STATUS
EFIAPI
copy: start with aligned 32-bit chunks, then byte remainder(
  VOID
);

EFI_STATUS
EFIAPI
= (Size & 3);  // remainder after 32-bit copies(
  VOID
);

EFI_STATUS
EFIAPI
the actual binary, the remainder copy uses qmemcpy for remainder of size % 4.(
  VOID
);

EFI_STATUS
EFIAPI
Services Table pointer retrieval (via IDTR)(
  VOID
);

EFI_STATUS
EFIAPI
IDTR to find the base of the IDT(
  VOID
);

EFI_STATUS
EFIAPI
(&Idtr);(
  VOID
);

EFI_STATUS
EFIAPI
PEI Services Table pointer is stored at offset -4 from the IDT base.(
  VOID
);

EFI_STATUS
EFIAPI
is a standard PEI Services Table Pointer Library mechanism for IA32.(
  VOID
);

EFI_STATUS
EFIAPI
= *(EFI_PEI_SERVICES ***)(Idtr.Base - 4);(
  VOID
);

EFI_STATUS
EFIAPI
IDTR register (SIDT instruction wrapper)(
  VOID
);

EFI_STATUS
EFIAPI
Database access(
  VOID
);

EFI_STATUS
EFIAPI
the PCD database pointer by locating the PCD PPI via(
  VOID
);

EFI_STATUS
EFIAPI
Services' LocatePpi.(
  VOID
);

EFI_STATUS
EFIAPI
*(
  VOID
);

EFI_STATUS
EFIAPI
PCD database pointer via PEI PCD PPI Locate(
  VOID
);

EFI_STATUS
EFIAPI
function locates the PCD PPI (not PCD database directly) and(
  VOID
);

EFI_STATUS
EFIAPI
the PPI interface. It is used to get PcdPpi, which is then(
  VOID
);

EFI_STATUS
EFIAPI
to call PcdGetX functions.(
  VOID
);

EFI_STATUS
EFIAPI
to get the PCD PPI interface(
  VOID
);

EFI_STATUS
EFIAPI
= (*PeiServices)->LocatePpi ((
  VOID
);

EFI_STATUS
EFIAPI
uses gPeiPcdPpiGuid(
  VOID
);

EFI_STATUS
EFIAPI
Express base address retrieval (from PCD)(
  VOID
);

EFI_STATUS
EFIAPI
the PciExpressBaseAddress from PCD. Uses the PCD PPI to call(
  VOID
);

EFI_STATUS
EFIAPI
PCI Express configuration space (ECAM).(
  VOID
);

EFI_STATUS
EFIAPI
PcdGetPtr(token_value=5) to retrieve PcdPciExpressBaseAddress.(
  VOID
);

EFI_STATUS
EFIAPI
token value 5 corresponds to fixed-at-build PCD(
  VOID
);

EFI_STATUS
EFIAPI
in typical EDK2 builds.(
  VOID
);

EFI_STATUS
EFIAPI
PcdGetPtr[4] (5);(
  VOID
);

EFI_STATUS
EFIAPI
Express MMIO config space access - Read8(
  VOID
);

EFI_STATUS
EFIAPI
address: must have bits [31:28] clear ( < 256MB offset )(
  VOID
);

EFI_STATUS
EFIAPI
((Address & 0xF0000000) != 0) {(
  VOID
);

EFI_STATUS
EFIAPI
Express MMIO config space access - Write8(
  VOID
);

EFI_STATUS
EFIAPI
Express MMIO config space access - Read16(
  VOID
);

EFI_STATUS
EFIAPI
Express MMIO config space access - Write16(
  VOID
);

EFI_STATUS
EFIAPI
Express MMIO config space access - Read32(
  VOID
);

EFI_STATUS
EFIAPI
Express MMIO config space access - Write32(
  VOID
);

EFI_STATUS
EFIAPI
Express Atomic OR - 8-bit(
  VOID
);

EFI_STATUS
EFIAPI
Express Atomic OR - 16-bit(
  VOID
);

EFI_STATUS
EFIAPI
Express Atomic OR - 32-bit(
  VOID
);

EFI_STATUS
EFIAPI
memory access helpers(
  VOID
);

EFI_STATUS
EFIAPI
error status (CMOS-based)(
  VOID
);

EFI_STATUS
EFIAPI
the platform error status from CMOS register 0x4A.(
  VOID
);

EFI_STATUS
EFIAPI
is used by the ASSERT infrastructure to decide whether to(
  VOID
);

EFI_STATUS
EFIAPI
or halt on assertion failure.(
  VOID
);

EFI_STATUS
EFIAPI
- No error(
  VOID
);

EFI_STATUS
EFIAPI
- Error status cleared(
  VOID
);

EFI_STATUS
EFIAPI
current CMOS index register (0x70), preserving bit 7 (NMI disable)(
  VOID
);

EFI_STATUS
EFIAPI
= IoRead8 (0x70);(
  VOID
);

EFI_STATUS
EFIAPI
a hardware register (at fixed address 0xFDAF0490) for(
  VOID
);

EFI_STATUS
EFIAPI
error info(
  VOID
);

EFI_STATUS
EFIAPI
= (*(volatile UINT8 *)0xFDAF0490 & 2) | 1;(
  VOID
);

EFI_STATUS
EFIAPI
Status values 1 and 2 are used:(
  VOID
);

EFI_STATUS
EFIAPI
-> EFI_DEVICE_ERROR (recoverable)(
  VOID
);

EFI_STATUS
EFIAPI
-> more severe error(
  VOID
);

EFI_STATUS
EFIAPI
(Status) {(
  VOID
);

EFI_STATUS
EFIAPI
was 0xFF (cleared)(
  VOID
);

EFI_STATUS
EFIAPI
functions use the PCD database to call into the DebugLib(
  VOID
);

EFI_STATUS
EFIAPI
installed as a PPI. The PCD database pointer at(
  VOID
);

EFI_STATUS
EFIAPI
+4 contains the assertion/debug message handler function.(
  VOID
);

EFI_STATUS
EFIAPI
the standardized DebugLib was widely used.(
  VOID
);

EFI_STATUS
EFIAPI
the ASSERT handler from PCD database (at offset +4)(
  VOID
);

EFI_STATUS
EFIAPI
the DEBUG handler from PCD database (at offset +4)(
  VOID
);

#endif /* __PCATSINGLESEGMENTPCICFG2PEI_H__ */