/** @file
  PciBus.h -- Header for PciBus

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __PCIBUS_H__
#define __PCIBUS_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
PciBusEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
ProcessDriverInit(
  VOID
);

EFI_STATUS
EFIAPI
PciBusDriverBindingSupported(
  VOID
);

EFI_STATUS
EFIAPI
PciBusDriverBindingStart(
  VOID
);

EFI_STATUS
EFIAPI
PciBusDriverBindingStop(
  VOID
);

EFI_STATUS
EFIAPI
PciBusEnumerateBus(
  VOID
);

EFI_STATUS
EFIAPI
PciBusEnumerateDevice(
  VOID
);

EFI_STATUS
EFIAPI
PciBusInitDevice(
  VOID
);

EFI_STATUS
EFIAPI
PciBusParseBar(
  VOID
);

EFI_STATUS
EFIAPI
PciBusParseExpBar(
  VOID
);

EFI_STATUS
EFIAPI
PciBusCalculateBrgResources(
  VOID
);

EFI_STATUS
EFIAPI
PciBusOptimizeBrgResources(
  VOID
);

EFI_STATUS
EFIAPI
PciBusArrangeFixResources(
  VOID
);

EFI_STATUS
EFIAPI
PciBusAllocateResource(
  VOID
);

EFI_STATUS
EFIAPI
PcieSetLinkProperties(
  VOID
);

EFI_STATUS
EFIAPI
PcieSetDeviceProperties(
  VOID
);

EFI_STATUS
EFIAPI
PcieInitLink(
  VOID
);

EFI_STATUS
EFIAPI
PcieLinkTraining(
  VOID
);

EFI_STATUS
EFIAPI
PcieCollectCaps(
  VOID
);

EFI_STATUS
EFIAPI
PcieSetAspm(
  VOID
);

EFI_STATUS
EFIAPI
Pcie2SetLinkProperties(
  VOID
);

EFI_STATUS
EFIAPI
Pcie2SetDeviceProperties(
  VOID
);

EFI_STATUS
EFIAPI
SriovProbeDevice(
  VOID
);

EFI_STATUS
EFIAPI
PciBusInstallPciIo(
  VOID
);

EFI_STATUS
EFIAPI
PciBusProcessRomImage(
  VOID
);

EFI_STATUS
EFIAPI
PciBusS3BootScriptSave(
  VOID
);

EFI_STATUS
EFIAPI
PciBusS3BootScriptExecute(
  VOID
);

EFI_STATUS
EFIAPI
PciBusAllocateDmaBuffer(
  VOID
);

EFI_STATUS
EFIAPI
PciBusDebugPrint(
  VOID
);

EFI_STATUS
EFIAPI
PciBusAssertReport(
  VOID
);

EFI_STATUS
EFIAPI
PciBusFindGuidInHob(
  VOID
);

EFI_STATUS
EFIAPI
PciBusPciExpressAddr(
  VOID
);

EFI_STATUS
EFIAPI
PciBusGetNextFunction(
  VOID
);

EFI_STATUS
EFIAPI
PciBusIsPciDevicePresent(
  VOID
);

EFI_STATUS
EFIAPI
PciBusSkipNicBySlot(
  VOID
);

EFI_STATUS
EFIAPI
PciBusCheckNicDriverBinding(
  VOID
);

EFI_STATUS
EFIAPI
used:(
  VOID
);

EFI_STATUS
EFIAPI
(e:\hs\AmiModulePkg\Library\AmiPciExpressLib)(
  VOID
);

EFI_STATUS
EFIAPI
(e:\hs\AmiModulePkg\Library\AmiSriovLib)(
  VOID
);

EFI_STATUS
EFIAPI
(e:\hs\AmiModulePkg\Library\AmiPciBusLib)(
  VOID
);

EFI_STATUS
EFIAPI
(e:\hs\AmiCRBPkg\Chipset\SB\SbPciHotPlugLib)(
  VOID
);

EFI_STATUS
EFIAPI
layout:(
  VOID
);

EFI_STATUS
EFIAPI
- 0x001DCC: Driver Entry, Protocol Registration(
  VOID
);

EFI_STATUS
EFIAPI
- 0x00599C: Device Enumeration, Bridge Setup(
  VOID
);

EFI_STATUS
EFIAPI
- 0x00B944: BAR Handling, SDL, Resource Allocation(
  VOID
);

EFI_STATUS
EFIAPI
- 0x00E5E0: Bus Scan, PciIo Installation, Option ROM(
  VOID
);

EFI_STATUS
EFIAPI
- 0x010C10: Option ROM, Platform Policy, Reset(
  VOID
);

EFI_STATUS
EFIAPI
- 0x018B58: PCI Express (Gen2/Gen3/Gen4 Link & Device Config)(
  VOID
);

EFI_STATUS
EFIAPI
- 0x01A84C: PciInitProtocol, IOMMU/DMA(
  VOID
);

EFI_STATUS
EFIAPI
- 0x01D0E0: S3 Boot Script(
  VOID
);

EFI_STATUS
EFIAPI
- 0x024B00: String table (.rdata)(
  VOID
);

EFI_STATUS
EFIAPI
ENTRY POINT(
  VOID
);

EFI_STATUS
EFIAPI
ProcessDriverInit() for DXE protocol init(
  VOID
);

EFI_STATUS
EFIAPI
PciBusDriverBindingSupported() to install driver binding(
  VOID
);

EFI_STATUS
EFIAPI
PciBusUnload() on failure(
  VOID
);

EFI_STATUS
EFIAPI
INITIALIZATION(
  VOID
);

EFI_STATUS
EFIAPI
gImageHandle, gST, gBS, gRT(
  VOID
);

EFI_STATUS
EFIAPI
PciBusInitDmaProtection()(
  VOID
);

EFI_STATUS
EFIAPI
CPU flags, cache control(
  VOID
);

EFI_STATUS
EFIAPI
for APs to finish initialization(
  VOID
);

EFI_STATUS
EFIAPI
BINDING PROTOCOL(
  VOID
);

EFI_STATUS
EFIAPI
PCI root bridge I/O protocol on controller(
  VOID
);

EFI_STATUS
EFIAPI
for ACPI device path(
  VOID
);

EFI_STATUS
EFIAPI
cache line size from CPU info HOB(
  VOID
);

EFI_STATUS
EFIAPI
PciRootBridgeIo protocol(
  VOID
);

EFI_STATUS
EFIAPI
root bridge instance(
  VOID
);

EFI_STATUS
EFIAPI
PciBusEnumerateBus() to scan devices(
  VOID
);

EFI_STATUS
EFIAPI
and uninstalls protocols for all child devices(
  VOID
);

EFI_STATUS
EFIAPI
ENUMERATION(
  VOID
);

EFI_STATUS
EFIAPI
all PCI buses starting from bus 0(
  VOID
);

EFI_STATUS
EFIAPI
PCI devices and bridges(
  VOID
);

EFI_STATUS
EFIAPI
bus numbers to bridges (Bus OOR = Out Of Range handling)(
  VOID
);

EFI_STATUS
EFIAPI
PciBusEnumerateDevice() for each discovered device(
  VOID
);

EFI_STATUS
EFIAPI
gEfiPciEnumerationCompleteProtocolGuid at end(
  VOID
);

EFI_STATUS
EFIAPI
VID/DID, checks vendor/device presence(
  VOID
);

EFI_STATUS
EFIAPI
PciBusCreatePciDeviceNode() to allocate device struct(
  VOID
);

EFI_STATUS
EFIAPI
PciBusGetPciDeviceData() to read config space(
  VOID
);

EFI_STATUS
EFIAPI
PciBusGetDeviceCapability() to parse capabilities(
  VOID
);

EFI_STATUS
EFIAPI
PciBusLocateSdlData() for SDL slot mapping(
  VOID
);

EFI_STATUS
EFIAPI
PciBusProbeDeviceBar() to read BARs(
  VOID
);

EFI_STATUS
EFIAPI
discovered device via PciBusReportDevice()(
  VOID
);

EFI_STATUS
EFIAPI
device attributes from SDL configuration(
  VOID
);

EFI_STATUS
EFIAPI
PCI attributes via PciBusPciRead/PciBusPciWrite(
  VOID
);

EFI_STATUS
EFIAPI
device-specific initialization phases(
  VOID
);

EFI_STATUS
EFIAPI
HANDLING(
  VOID
);

EFI_STATUS
EFIAPI
through 6 standard PCI BARs(
  VOID
);

EFI_STATUS
EFIAPI
BAR type (IO, MMIO32, MMIO64, PMEM32, PMEM64)(
  VOID
);

EFI_STATUS
EFIAPI
BAR size and alignment(
  VOID
);

EFI_STATUS
EFIAPI
64-bit BARs spanning two registers(
  VOID
);

EFI_STATUS
EFIAPI
Extended BARs (PCI Express capability)(
  VOID
);

EFI_STATUS
EFIAPI
>4GB MMIO BARs(
  VOID
);

EFI_STATUS
EFIAPI
ALLOCATION(
  VOID
);

EFI_STATUS
EFIAPI
resource requirements per bridge(
  VOID
);

EFI_STATUS
EFIAPI
IO, MMIO32, MMIO64, PMEM32, PMEM64 per bridge(
  VOID
);

EFI_STATUS
EFIAPI
PciBusSortBridgeResources() for ordering(
  VOID
);

EFI_STATUS
EFIAPI
PciBusOptimizeBrgResources() for bridge resource optimization(
  VOID
);

EFI_STATUS
EFIAPI
PciBusInsertSortedBar() for sorted resource insertion(
  VOID
);

EFI_STATUS
EFIAPI
bridge resource windows(
  VOID
);

EFI_STATUS
EFIAPI
device and bridge BARs by type(
  VOID
);

EFI_STATUS
EFIAPI
adjacent resources when possible(
  VOID
);

EFI_STATUS
EFIAPI
FIXED resources (pre-assigned by platform)(
  VOID
);

EFI_STATUS
EFIAPI
alignment (IO min 4K, MMIO min 1MB)(
  VOID
);

EFI_STATUS
EFIAPI
fixed bridge resource requirements(
  VOID
);

EFI_STATUS
EFIAPI
IO and memory space to all bridges(
  VOID
);

EFI_STATUS
EFIAPI
non-contiguous resource allocation(
  VOID
);

EFI_STATUS
EFIAPI
AllocateIoSpace / AllocateMemorySpace primitives(
  VOID
);

EFI_STATUS
EFIAPI
each PCI device for resource requirements(
  VOID
);

EFI_STATUS
EFIAPI
"Probing PCI Device" + current resource state(
  VOID
);

EFI_STATUS
EFIAPI
EXPRESS LINK TRAINING & CONFIGURATION (Gen1/Gen2/Gen3/Gen4)(
  VOID
);

EFI_STATUS
EFIAPI
PCIe link capabilities via LINK_CAP/LINK_CTRL2(
  VOID
);

EFI_STATUS
EFIAPI
LNK_CNT register and applies settings(
  VOID
);

EFI_STATUS
EFIAPI
link control register with new values(
  VOID
);

EFI_STATUS
EFIAPI
LNK_CNT field breakdown:(
  VOID
);

EFI_STATUS
EFIAPI
(Bandwidth Init), BwMI, AuWi (Auto Width), CkPM, ExS (Extended Sync)(
  VOID
);

EFI_STATUS
EFIAPI
(Clock Common), Rtr (Retrain), LDis (Link Disable)(
  VOID
);

EFI_STATUS
EFIAPI
(Read Completion Boundary), ASPM(
  VOID
);

EFI_STATUS
EFIAPI
PCIe device capabilities (MaxPayload, MRRS, etc.)(
  VOID
);

EFI_STATUS
EFIAPI
DEV_CNT register, applies new settings(
  VOID
);

EFI_STATUS
EFIAPI
Tag, MaxPayload, Relaxed Ordering(
  VOID
);

EFI_STATUS
EFIAPI
DEV_CNT field breakdown(
  VOID
);

EFI_STATUS
EFIAPI
link for downstream ports(
  VOID
);

EFI_STATUS
EFIAPI
ARI (Alternative Routing ID) configuration(
  VOID
);

EFI_STATUS
EFIAPI
enable/disable based on platform policy(
  VOID
);

EFI_STATUS
EFIAPI
link as needed(
  VOID
);

EFI_STATUS
EFIAPI
PCIe link training (recovery state handling)(
  VOID
);

EFI_STATUS
EFIAPI
timeout per retry(
  VOID
);

EFI_STATUS
EFIAPI
EQ_STS (equalization status)(
  VOID
);

EFI_STATUS
EFIAPI
link on training failure(
  VOID
);

EFI_STATUS
EFIAPI
and displays all PCIe capabilities:(
  VOID
);

EFI_STATUS
EFIAPI
(capability version, port type, slot)(
  VOID
);

EFI_STATUS
EFIAPI
(device capabilities including R2, FR, PowerS, etc.)(
  VOID
);

EFI_STATUS
EFIAPI
(link capabilities: speed, width, ASPM)(
  VOID
);

EFI_STATUS
EFIAPI
(slot capabilities)(
  VOID
);

EFI_STATUS
EFIAPI
(root complex capabilities)(
  VOID
);

EFI_STATUS
EFIAPI
ASPM (Active State Power Management)(
  VOID
);

EFI_STATUS
EFIAPI
upstream/downstream port latency(
  VOID
);

EFI_STATUS
EFIAPI
PCI_SETUP_DONT_TOUCH for ASPM(
  VOID
);

EFI_STATUS
EFIAPI
best ASPM state for the link(
  VOID
);

EFI_STATUS
EFIAPI
LNK_CNT2 register (CmDe, CmSOS, ECm, TrM, ...)(
  VOID
);

EFI_STATUS
EFIAPI
Gen2 link settings(
  VOID
);

EFI_STATUS
EFIAPI
DEV_CNT2 (EEPrB, LTR, IDO, ARI, Completion Timeout)(
  VOID
);

EFI_STATUS
EFIAPI
SR-IOV capable devices(
  VOID
);

EFI_STATUS
EFIAPI
ARI capability, page size(
  VOID
);

EFI_STATUS
EFIAPI
Virtual Functions (VFs)(
  VOID
);

EFI_STATUS
EFIAPI
mMaxBusFound after VF enumeration(
  VOID
);

EFI_STATUS
EFIAPI
ROM(
  VOID
);

EFI_STATUS
EFIAPI
EFI_PCI_IO_PROTOCOL on device handle(
  VOID
);

EFI_STATUS
EFIAPI
OpROM enable/disable(
  VOID
);

EFI_STATUS
EFIAPI
and dispatches Option ROM images(
  VOID
);

EFI_STATUS
EFIAPI
OEM program devices(
  VOID
);

EFI_STATUS
EFIAPI
BusOvr (Bus Override) and LoadFile2 protocols(
  VOID
);

EFI_STATUS
EFIAPI
ROM file location from SDL data(
  VOID
);

EFI_STATUS
EFIAPI
ROM image from specified location(
  VOID
);

EFI_STATUS
EFIAPI
BOOT SCRIPT SUPPORT(
  VOID
);

EFI_STATUS
EFIAPI
PCI configuration to S3 boot script(
  VOID
);

EFI_STATUS
EFIAPI
IO, memory, PCI CFG operations for S3 resume(
  VOID
);

EFI_STATUS
EFIAPI
S3 boot script entries(
  VOID
);

EFI_STATUS
EFIAPI
label, IO write, mem write, PCI CFG write operations(
  VOID
);

EFI_STATUS
EFIAPI
dispatch entries for early S3 restore(
  VOID
);

EFI_STATUS
EFIAPI
DMA-safe buffer via IoMmu protocol(
  VOID
);

EFI_STATUS
EFIAPI
DMA remap attributes(
  VOID
);

EFI_STATUS
EFIAPI
/ PLATFORM(
  VOID
);

EFI_STATUS
EFIAPI
group/pin error strings indicate platform-specific GPIO configuration(
  VOID
);

EFI_STATUS
EFIAPI
LPC device ID validation for chipset SKU detection(
  VOID
);

EFI_STATUS
EFIAPI
FUNCTIONS(
  VOID
);

EFI_STATUS
EFIAPI
around DebugPrint()(
  VOID
);

EFI_STATUS
EFIAPI
mask controls output (0x400000=info, 0x80000000=error)(
  VOID
);

EFI_STATUS
EFIAPI
assertion failures(
  VOID
);

EFI_STATUS
EFIAPI
file:line triple from UEFI debug infrastructure(
  VOID
);

EFI_STATUS
EFIAPI
GetNextGuidHob() for matching GUID in HOB list(
  VOID
);

EFI_STATUS
EFIAPI
MMIO address for PCIe configuration access(
  VOID
);

EFI_STATUS
EFIAPI
on MCFG table base address(
  VOID
);

EFI_STATUS
EFIAPI
next PCI function (multi-function device support)(
  VOID
);

EFI_STATUS
EFIAPI
vendor ID != 0xFFFF to detect device presence(
  VOID
);

EFI_STATUS
EFIAPI
NIC BYPASS (HR650X platform specific)(
  VOID
);

EFI_STATUS
EFIAPI
multiple Riser configurations:(
  VOID
);

EFI_STATUS
EFIAPI
ports: RP 0x1A, 0x2A, 0x3A, 0x3C, 0x1C, 0x2C(
  VOID
);

EFI_STATUS
EFIAPI
PXE driver binding on NICs behind specified slots(
  VOID
);

EFI_STATUS
EFIAPI
network device before PXE driver binding(
  VOID
);

EFI_STATUS
EFIAPI
NICs with >4 ports(
  VOID
);

#endif /* __PCIBUS_H__ */