/** @file
  PciRootBridge.h -- Header for PciRootBridge

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __PCIROOTBRIDGE_H__
#define __PCIROOTBRIDGE_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
PciHbNotifyPhase(
  VOID
);

EFI_STATUS
EFIAPI
PciHbGetNextRootBridge(
  VOID
);

EFI_STATUS
EFIAPI
PciHbGetAllocAttributes(
  VOID
);

EFI_STATUS
EFIAPI
PciHbStartBusEnumeration(
  VOID
);

EFI_STATUS
EFIAPI
PciHbSetBusNumbers(
  VOID
);

EFI_STATUS
EFIAPI
PciHbSubmitResources(
  VOID
);

EFI_STATUS
EFIAPI
PciHbGetProposedResources(
  VOID
);

EFI_STATUS
EFIAPI
PciHbPreprocessController(
  VOID
);

EFI_STATUS
EFIAPI
ModuleEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
PciHostBridgeEntry(
  VOID
);

EFI_STATUS
EFIAPI
PciHostBridgeReserveCspResources(
  VOID
);

EFI_STATUS
EFIAPI
PciHostBridgeSetupConfig(
  VOID
);

EFI_STATUS
EFIAPI
PciHostBridgeConvertMemory(
  VOID
);

EFI_STATUS
EFIAPI
LocateDxeServicesTable(
  VOID
);

EFI_STATUS
EFIAPI
LocateBoardInfo2Protocol(
  VOID
);

EFI_STATUS
EFIAPI
PciHostBridgeFindSdlRecordIndex(
  VOID
);

EFI_STATUS
EFIAPI
PciHostBridgeGetRootBridges(
  VOID
);

EFI_STATUS
EFIAPI
Variables(
  VOID
);

EFI_STATUS
EFIAPI
BootServices / Runtime / DXE core handles (initialized in sub_3BC)(
  VOID
);

EFI_STATUS
EFIAPI
gImageHandle = NULL;     // sub_3BC saves ImageHandle(
  VOID
);

EFI_STATUS
EFIAPI
saves SystemTable(
  VOID
);

EFI_STATUS
EFIAPI
saves BS(
  VOID
);

EFI_STATUS
EFIAPI
saves RT(
  VOID
);

EFI_STATUS
EFIAPI
Services (qword_184F0)(
  VOID
);

EFI_STATUS
EFIAPI
bridge tracking(
  VOID
);

EFI_STATUS
EFIAPI
-- number of host bridges(
  VOID
);

EFI_STATUS
EFIAPI
-- allocated HB private data array (168 bytes per entry)(
  VOID
);

EFI_STATUS
EFIAPI
gHostBrgCount       = 0;(
  VOID
);

EFI_STATUS
EFIAPI
PCI USRA handle (PCIE_SEG_BUS_TABLE / MMIO PCI cfg access)(
  VOID
);

EFI_STATUS
EFIAPI
//(
  VOID
);

EFI_STATUS
EFIAPI
protocol (qword_18480)(
  VOID
);

EFI_STATUS
EFIAPI
*gpPcdProtocol       = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
(qword_18488)(
  VOID
);

EFI_STATUS
EFIAPI
SDL (System Description Layer) board data(
  VOID
);

EFI_STATUS
EFIAPI
*gpBoardInfo2Protocol = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
host bridge data pointer (from BoardInfo2 protocol)(
  VOID
);

EFI_STATUS
EFIAPI
configuration buffer (from UEFI variable "Setup")(
  VOID
);

EFI_STATUS
EFIAPI
-- 7 bytes: [0]=PciHot, [1]=PciAer, [2]=PciHpc, [3]=Above4G, [4-5]=?(
  VOID
);

EFI_STATUS
EFIAPI
*gpSetupConfig       = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
(qword_18430)(
  VOID
);

EFI_STATUS
EFIAPI
*gpIoMmuProtocol     = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
(qword_18420)(
  VOID
);

EFI_STATUS
EFIAPI
*gpAmiBoardPciInit   = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
event handle (qword_18560)(
  VOID
);

EFI_STATUS
EFIAPI
gReadyToBootEvent   = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
Handoff data (qword_18440 / qword_18438)(
  VOID
);

EFI_STATUS
EFIAPI
gSmmHandoffHostCnt  = 0;(
  VOID
);

EFI_STATUS
EFIAPI
function declarations (renamed from sub_XXXX)(
  VOID
);

/// saves boot services/runtime/dxe tables
EFI_STATUS
EFIAPI
library init function(
  VOID
);

EFI_STATUS
EFIAPI
EFI_STATUS(
  VOID
);

EFI_STATUS
EFIAPI
dispatch function declarations (HB protocol)(
  VOID
);

EFI_STATUS
EFIAPI
EFIAPI(
  VOID
);

EFI_STATUS
EFIAPI
DXE driver entry point. Called by firmware.(
  VOID
);

EFI_STATUS
EFIAPI
to PciHostBridgeEntry().(
  VOID
);

EFI_STATUS
EFIAPI
globals: ImageHandle, gST, gBS, gRT, gDS, also initializes(
  VOID
);

EFI_STATUS
EFIAPI
and PCD library. Called once at entry.(
  VOID
);

EFI_STATUS
EFIAPI
UEFI core handles(
  VOID
);

EFI_STATUS
EFIAPI
DXE Services Table (gDS)(
  VOID
);

EFI_STATUS
EFIAPI
= EfiGetSystemConfigurationTable(&gEfiDxeServicesTableGuid, &gDS);(
  VOID
);

EFI_STATUS
EFIAPI
PCD protocol (mPcd)(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->LocateProtocol(&gPcdProtocolGuid, NULL, &gpPcdProtocol);(
  VOID
);

EFI_STATUS
EFIAPI
MM PCI USRA (PCIE_SEG_BUS_TABLE)(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->LocateProtocol(&gAmiPcieSegBusTableGuid, NULL, &gpPciUsra);(
  VOID
);

EFI_STATUS
EFIAPI
PCIE_SEG_BUS_TABLE size is sufficient(
  VOID
);

EFI_STATUS
EFIAPI
driver logic. The entry function:(
  VOID
);

EFI_STATUS
EFIAPI
module version banner(
  VOID
);

EFI_STATUS
EFIAPI
((EFI_D_INFO(
  VOID
);

EFI_STATUS
EFIAPI
AMI_BOARD_INFO2_PROTOCOL to get SDL host bridge data(
  VOID
);

EFI_STATUS
EFIAPI
= LocateBoardInfo2Protocol ();(
  VOID
);

EFI_STATUS
EFIAPI
active host bridges (SDL records with bit[57] & 1 set)(
  VOID
);

EFI_STATUS
EFIAPI
= 0;(
  VOID
);

EFI_STATUS
EFIAPI
array of active HB SDL record pointers(
  VOID
);

EFI_STATUS
EFIAPI
be overwritten(
  VOID
);

EFI_STATUS
EFIAPI
chipset-specific (CSP) resources(
  VOID
);

EFI_STATUS
EFIAPI
((EFI_D_INFO, " HB: Reserve CSP Resources( ImageHandle=0x%X)\n", ImageHandle));(
  VOID
);

EFI_STATUS
EFIAPI
global resources: setup config (7 bytes), HB private array(
  VOID
);

EFI_STATUS
EFIAPI
= AllocateZeroPool (7);(
  VOID
);

EFI_STATUS
EFIAPI
platform setup config from UEFI "Setup" variable(
  VOID
);

EFI_STATUS
EFIAPI
= PciHostBridgeSetupConfig ();(
  VOID
);

EFI_STATUS
EFIAPI
all unallocated memory to MMIO using GCD services(
  VOID
);

EFI_STATUS
EFIAPI
= PciHostBridgeConvertMemory (ImageHandle);(
  VOID
);

EFI_STATUS
EFIAPI
AmiBoardPciInitProtocol (for board-specific PCI init callbacks)(
  VOID
);

EFI_STATUS
EFIAPI
(gpAmiBoardPciInit == NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
over each active host bridge(
  VOID
);

EFI_STATUS
EFIAPI
(HostBrgIndex = 0; HostBrgIndex < gHostBrgCount; HostBrgIndex++) {(
  VOID
);

EFI_STATUS
EFIAPI
SDL record index for this host bridge(
  VOID
);

EFI_STATUS
EFIAPI
(SdlRecord != NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
in HB private context(
  VOID
);

EFI_STATUS
EFIAPI
attributes supported:(
  VOID
);

EFI_STATUS
EFIAPI
protocol dispatch function table(
  VOID
);

EFI_STATUS
EFIAPI
disable above-4G decode attribute(
  VOID
);

EFI_STATUS
EFIAPI
(!((UINT8*)gpSetupConfig)[3]) {(
  VOID
);

EFI_STATUS
EFIAPI
chipset-specific common function: Initialize HB (Step 12, Cmd 1)(
  VOID
);

EFI_STATUS
EFIAPI
= PciHostBridgeCallCmnFn (Private, 12, 1);(
  VOID
);

EFI_STATUS
EFIAPI
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL protocol(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->InstallProtocolInterface ((
  VOID
);

EFI_STATUS
EFIAPI
root bridges for this host bridge from SDL(
  VOID
);

EFI_STATUS
EFIAPI
= PciHostBridgeGetRootBridges ((
  VOID
);

EFI_STATUS
EFIAPI
per-previous-host RB counts for UID assignment(
  VOID
);

EFI_STATUS
EFIAPI
(HostBrgIndex > 0) {(
  VOID
);

EFI_STATUS
EFIAPI
no root bridges found, skip HB processing(
  VOID
);

EFI_STATUS
EFIAPI
(RbCount == 0) {(
  VOID
);

EFI_STATUS
EFIAPI
each root bridge found, allocate and initialize a root bridge(
  VOID
);

EFI_STATUS
EFIAPI
context of 480 bytes.(
  VOID
);

EFI_STATUS
EFIAPI
(RbIndex = 0; RbIndex < RbCount; RbIndex++) {(
  VOID
);

EFI_STATUS
EFIAPI
root bridge context (480 bytes total)(
  VOID
);

EFI_STATUS
EFIAPI
= AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_PRIVATE));(
  VOID
);

EFI_STATUS
EFIAPI
root bridge: link to host bridge, get SDL record, etc.(
  VOID
);

EFI_STATUS
EFIAPI
SDL record index for this root bridge(
  VOID
);

EFI_STATUS
EFIAPI
(RbSdlRecord != NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
supported: from SDL entry offset 16(
  VOID
);

EFI_STATUS
EFIAPI
name buffer: from SDL entry offset 24(
  VOID
);

EFI_STATUS
EFIAPI
above-4G decode is enabled (setup[3] true), add 4G decode attribute(
  VOID
);

EFI_STATUS
EFIAPI
(((UINT8*)gpSetupConfig)[3]) {(
  VOID
);

EFI_STATUS
EFIAPI
chipset-specific: Initialize RB (Step 13, Cmd 2)(
  VOID
);

EFI_STATUS
EFIAPI
= PciHostBridgeCallCmnFn (RbPrivate, 13, 2);(
  VOID
);

EFI_STATUS
EFIAPI
RB is flagged as NOT present, skip further initialization(
  VOID
);

EFI_STATUS
EFIAPI
(*(UINT8*)((UINT8*)RbPrivate + 243)) {(
  VOID
);

EFI_STATUS
EFIAPI
protocol dispatch table for RootBridgeIo(
  VOID
);

EFI_STATUS
EFIAPI
segment number from SDL(
  VOID
);

EFI_STATUS
EFIAPI
initial bus range ACPI descriptor (46 bytes)(
  VOID
);

EFI_STATUS
EFIAPI
QWord Resource Descriptor:(
  VOID
);

EFI_STATUS
EFIAPI
= 0x8A (Small: 0x8A is QWord descriptor for bus range)(
  VOID
);

EFI_STATUS
EFIAPI
= 43(
  VOID
);

EFI_STATUS
EFIAPI
= secondary bus number (RbSdlRecord[8])(
  VOID
);

EFI_STATUS
EFIAPI
= subordinate bus number (from next SDL or 0xFF)(
  VOID
);

EFI_STATUS
EFIAPI
= _MAX - _MIN + 1(
  VOID
);

EFI_STATUS
EFIAPI
Address Space Descriptor(
  VOID
);

EFI_STATUS
EFIAPI
BusDescriptor[2] = 2;     // bus range type(
  VOID
);

EFI_STATUS
EFIAPI
*(UINT64*)(BusDescriptor + 22) = 0xFF; // _MAX (may be adjusted if next bridge)(
  VOID
);

EFI_STATUS
EFIAPI
}(
  VOID
);

EFI_STATUS
EFIAPI
chipset-specific: Initialize Bus Range (Step 14, Cmd 2)(
  VOID
);

EFI_STATUS
EFIAPI
= *(UINT16*)(RbPrivate->BusDescriptor + 14);(
  VOID
);

EFI_STATUS
EFIAPI
ACPI device path (_SB scope H[host]R[ Rb](AslName)BSH )(
  VOID
);

EFI_STATUS
EFIAPI
install it via RuntimeServices->SetVariable or similar(
  VOID
);

EFI_STATUS
EFIAPI
bus descriptor to RB resource list(
  VOID
);

EFI_STATUS
EFIAPI
= PciRootBridgeAppendResource (RbPrivate, BusDescriptor);(
  VOID
);

EFI_STATUS
EFIAPI
and install DEVICE_PATH protocol with ACPI _UID(
  VOID
);

EFI_STATUS
EFIAPI
*(UINT32*)((UINT8*)PathData + 4)  = 0x0A034810; // UID(
  VOID
);

EFI_STATUS
EFIAPI
+ end(
  VOID
);

EFI_STATUS
EFIAPI
both RB_IO and DevicePath protocols together(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->InstallMultipleProtocolInterfaces ((
  VOID
);

EFI_STATUS
EFIAPI
protocol(
  VOID
);

EFI_STATUS
EFIAPI
path(
  VOID
);

EFI_STATUS
EFIAPI
hot-plug controller support is enabled (setup[2] == 1)(
  VOID
);

EFI_STATUS
EFIAPI
HPC (Hot-Plug Controller) protocol(
  VOID
);

EFI_STATUS
EFIAPI
(((UINT8*)gpSetupConfig)[2] == 1) {(
  VOID
);

EFI_STATUS
EFIAPI
for each root bridge(
  VOID
);

EFI_STATUS
EFIAPI
for each host bridge(
  VOID
);

EFI_STATUS
EFIAPI
SMM Handoff protocol if not already installed(
  VOID
);

EFI_STATUS
EFIAPI
(gSmmHandoffHandle == NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
ReadyToBoot event(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->CreateEvent ((
  VOID
);

EFI_STATUS
EFIAPI
IOMMU protocol notification and close SMM lock event(
  VOID
);

EFI_STATUS
EFIAPI
= PciAccessCspRegisterIoMmuNotify ((
  VOID
);

EFI_STATUS
EFIAPI
for IOMMU protocol (gEdkiiIoMmuProtocolGuid)(
  VOID
);

EFI_STATUS
EFIAPI
(gpIoMmuProtocol == NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
GCD services to:(
  VOID
);

EFI_STATUS
EFIAPI
before HB private data is installed.(
  VOID
);

EFI_STATUS
EFIAPI
DXE services table(
  VOID
);

EFI_STATUS
EFIAPI
= LocateDxeServicesTable ();(
  VOID
);

EFI_STATUS
EFIAPI
over each SDL host bridge entry, walk its memory resources(
  VOID
);

EFI_STATUS
EFIAPI
mark them in GCD. For each entry:(
  VOID
);

EFI_STATUS
EFIAPI
detail: This function processes 342-byte SDL records(
  VOID
);

EFI_STATUS
EFIAPI
at IOBase, MemBase, MemLen fields.(
  VOID
);

EFI_STATUS
EFIAPI
EFI_SUCCESS;(
  VOID
);

EFI_STATUS
EFIAPI
the UEFI "Setup" variable (which is an EFI variable with the(
  VOID
);

EFI_STATUS
EFIAPI
setup configuration GUID) to extract PCI-related setup options(
  VOID
);

EFI_STATUS
EFIAPI
a 7-byte global buffer (gpSetupConfig):(
  VOID
);

EFI_STATUS
EFIAPI
the "Setup" variable can't be read, defaults are set:(
  VOID
);

EFI_STATUS
EFIAPI
"Setup" variable (the platform setup variable)(
  VOID
);

EFI_STATUS
EFIAPI
= gRT->GetVariable ((
  VOID
);

EFI_STATUS
EFIAPI
not found; use defaults(
  VOID
);

EFI_STATUS
EFIAPI
the DXE memory services to:(
  VOID
);

EFI_STATUS
EFIAPI
handles the IO space in a similar manner.(
  VOID
);

EFI_STATUS
EFIAPI
after CSP resource reservation.(
  VOID
);

EFI_STATUS
EFIAPI
GCD memory map entries:(
  VOID
);

EFI_STATUS
EFIAPI
each entry that is free (unallocated) and within the(
  VOID
);

EFI_STATUS
EFIAPI
bridge's resource windows:(
  VOID
);

EFI_STATUS
EFIAPI
Helpers (internal)(
  VOID
);

EFI_STATUS
EFIAPI
(original sub_47D8 @ 0x47D8)(
  VOID
);

EFI_STATUS
EFIAPI
(original sub_4804 @ 0x4804)(
  VOID
);

EFI_STATUS
EFIAPI
(original sub_35D0 @ 0x35D0)(
  VOID
);

EFI_STATUS
EFIAPI
(original sub_4510 @ 0x4510)(
  VOID
);

EFI_STATUS
EFIAPI
the configuration table looking for the matching GUID(
  VOID
);

EFI_STATUS
EFIAPI
(i = 0; i < EntryCount; i++) {(
  VOID
);

EFI_STATUS
EFIAPI
(original sub_4B5C @ 0x4B5C)(
  VOID
);

EFI_STATUS
EFIAPI
LocateDxeServicesTable ((
  VOID
);

EFI_STATUS
EFIAPI
(original sub_365C @ 0x365C)(
  VOID
);

EFI_STATUS
EFIAPI
LocateBoardInfo2Protocol ((
  VOID
);

EFI_STATUS
EFIAPI
(original sub_3754 @ 0x3754)(
  VOID
);

EFI_STATUS
EFIAPI
PciHostBridgeFindSdlRecordIndex ((
  VOID
);

EFI_STATUS
EFIAPI
(original sub_37D0 @ 0x37D0)(
  VOID
);

EFI_STATUS
EFIAPI
PciHostBridgeGetRootBridges ((
  VOID
);

EFI_STATUS
EFIAPI
entries that belong to this bridge index (SDL[0]==BridgeIndex)(
  VOID
);

EFI_STATUS
EFIAPI
and fill output list(
  VOID
);

EFI_STATUS
EFIAPI
= (UINT64*)AllocatePool (8 * FoundEntries);(
  VOID
);

#endif /* __PCIROOTBRIDGE_H__ */