| Address | Name | Description |
|---|---|---|
| ModuleEntryPoint | ||
| DebugPrint | ||
| CMOS | RTC I/O ports and register indices | |
| FRB | timeout status memory-mapped IO address | |
| ServerSetup | variable byte offsets | |
| FRB | enable flag at offset 6 in ServerSetup data | |
| Timer | multiplier byte at offset 7 | |
| PEI_SERVICES | function table offsets (IA32 flat model) | |
| FRB | default timeout: 3600 * 100ms = 360 seconds = 6 minutes | |
| Each | unit = 100ms | |
| Local | FRB configuration structure (6 bytes) | |
| typedef | struct { | |
| GUID | external declarations (defined in .data section of the PE32) | |
| extern | EFI_GUID gEfiFirmwareVolumeBlock2ProtocolGuid; | |
| FRB | PPI descriptor (installed before exit) | |
| extern | EFI_PEI_PPI_DESCRIPTOR gPeiFrbPpiDescriptor; | |
| Function | prototypes | |
| EFI_STATUS | EFIAPI | |
| Validate | the PEI Services revision | |
| if | ((*PeiServices)->Hdr.Revision < PEI_SERVICES_REVISION) { | |
| Initialize | FRB config structure: enabled=TRUE, all zeros | |
| FrbEnabled | = TRUE; | |
| Locate | the AMI PlatformSetup PPI | |
| Status | = (*PeiServices)->LocatePpi ( | |
| Read | FRB setup configuration from ServerSetup NVRAM variable | |
| GetFrbSetupData | ((INT32)SystemTable, &FrbCfg, &FrbEnabled); | |
| Configure | FRB: set reset type bits to cold reset | |
| preserve | timeout value from ServerSetup | |
| Enable | FRB, preserve timeout | |
| Write | FRB config to NVRAM via platform setup PPI (SetVariable #36) | |
| Dummy | = 0; | |
| Clear | the FRB reset-pending variable (SetVariable #34) | |
| Install | FRB PPI to notify subsequent PEIMs | |
| return | (*PeiServices)->InstallPpi ( | |
| FRB | not enabled in ServerSetup | |
| return | EFI_INVALID_PARAMETER; | |
| Locate | Firmware Volume Block 2 protocol to access NVRAM | |
| Status | = (*PeiServices)->LocateProtocol ( | |
| FVB | not available: assert and report error | |
| AssertHandler | (0x80000000, "\nASSERT_EFI_ERROR (Status = %r)\n", Status); | |
| Read | ServerSetup variable (expect max 1072 bytes) | |
| VarSize | = 1072; | |
| Extract | FRB enable flag (byte offset 6 in ServerSetup data) | |
| Compute | timeout: 10 * byte at offset 7 | |
| Timeout | = FRB_TIMEOUT_SCALE (INT32)(UINT32 *)&VarData[FRB_VAR_TIMEOUT_BYTE]; | |
| Locate | EFI_PEI_DEBUG2_PPI | |
| if | ((*PeiServices)->LocatePpi ( | |
| Only | print assert if reset type allows it | |
| return | ((INT32 (__cdecl )(INT32, const CHAR8 , CHAR8 *))Result)( | |
| Save | bit 7 of CMOS index, set index to Status Register A (0x4A) | |
| RtcIdx | = IoRead8 (RTC_INDEX_PORT); | |
| Read | the reset type value from CMOS data port | |
| ResetValue | = IoRead8 (RTC_DATA_PORT); | |
| Interpret | the reset type: | |
| 0 | = Power-on (cold start) | |
| 1 | = Warm reset via FRB timeout logic | |
| if | ((UINT8)ResetValue <= 3) { | |
| Direct | interpretation for values 0-3 | |
| if | (ResetValue == 0) { | |
| 0x80000004 | = EFI_WARN_RESET_COLD? No, actually this is EFI_WARN_RESET_WARM | |
| Return | value: if ResetValue != 1 -> cold reset | |
| return | 0x80000004; // FRB reset: warm | |
| EFI_WARN_RESET_COLD | / FRB reset: cold | |
| Src | = &((CHAR8 *)Source)[Count - 1]; | |
| Remaining | = Count & 3; |
Generated by HR650X BIOS Decompilation Project