PiSmmCpuDxeSmm, 0172, 75 KB, SMM Core

Core SMM CPU driver for Skylake-SP Xeon processors. Initializes SMM execution environment, manages SMI dispatch with CPU-model-specific MSR feature handling (SNB/HSW/SKX, KNL, IVT), provides multi-processor initialization via SIPI/AP startup, programs SMM page tables and SMRR ranges, manages S3 resume transitions with paging mode detection (32-bit vs 64-bit), and implements per-CPU register tables for MSR/control register programming.

Key Functions: SmmInit (full initialization: SMM foundation, MP data, page tables, long mode, AP startup), SmiHandlerDispatch (CPU-model-aware MSR SMI dispatch), SmmRestoreCpu (S3 resume with SwitchStack or AsmDisablePaging64), InitPaging (SMRR programming + 4KB page tables in SMRAM), InitMp (ACPI CPU data allocation: MTRR table, GDTR/IDTR profile, per-CPU register tables), StartupAP/SendSmiIpi (INIT-SIPI-SIPI sequence and APIC ICR), ProgramRegisterTable (MSR/CR per-entry programming).

Protocols/Dependencies: EFI_SMM_ACCESS2_PROTOCOL, ACPI_CPU_DATA, CPUID leaves 0xB+1 for topology detection, xAPIC/x2APIC modes.

Platform: Intel Purley (Skylake-SP) / HR650X server, PurleySktPkg/Override/IA32FamilyCpuPkg/PiSmmCpuDxeSmm