PpmInitialize

Function Table

Address	Name	Description
	PpmInitializeEntryPoint
	PpmInitialize
	PpmInfoInit
	PpmIdleInit
	PpmPbfMsrConfig
	PpmEnergyEfficientTurboConfig
	PpmPackagePowerLimitConfig
	PpmPmaxOffsetSearch
	PpmBiosResetCpl
	SmmReadyToLockCallback
	ReadyToBootCallback
	InternalGetBootScriptTable
	InternalGetCpuConfigContext
	InternalGetRegAddr
	CpuidEx
	Cpuid
	ReadTsc
	CpuPause
	EnableInterrupts
	DisableInterrupts
	ReadEflags
	ZeroMemSafe
	PciRead32
	PciWrite32
	IoRead32
	IoRead16
	IoWrite16
	IoRead8
	IoWrite8
	BootScriptAllocate
	BootScriptCloseTable
	S3BootScriptSaveMsrWrite
	DebugPrintHandler
	AssertHandler
Global	data (gImageHandle, gST, gBS, gRT) are declared in
UefiBootServicesTableLib	and UefiRuntimeServicesTableLib headers.
STATIC	*EFI_MP_SERVICES_PROTOCOL mMpService = NULL;**
Module	Entry Point
Check	PPM enable flag
if	*((INT8)((UINT8* )GetPcdProtocol ()->GetPcd (PCD_TOKEN_PPM_TDP)) >= 0) {**
Main	PPM Initialization
Initialize	PPM Info structures (PpmInfo.c equivalent)
PpmInfoInit	();
Call	PPM MSR config on all APs, then BSP
Register	SmmReadyToLock event
Status	= gBootServices->CreateEvent (
PPM	Info Initialization
Read	CPUID
CpuidEx	(CPUID_VERSION_INFO, 0, &CpuidEax, NULL, NULL, NULL);
Locate	MP Service protocol
Status	= gBootServices->LocateProtocol (
Locate	PPM Info HOB
GuidHob	*= (GUID )TableData;**
Allocate	per-socket buffer
Status	= gBootServices->AllocatePool (
Locate	SMM Communication protocol
PPM	Configure TDP
PPM	MSR Configuration (per socket, per thread)
Get	BSP index
BspCpuIndex	= 0;
MSR_PPM_CURRENT_CONFIG	(0x1FC)
MsrValue	= AsmReadMsr64 (MSR_PPM_CURRENT_CONFIG);
MSR_PM_PBF_MISC_CTL	(0x603)
MsrValue	= AsmReadMsr64 (MSR_PM_PBF_MISC_CTL);
MSR_PM_PBF_CMD	(0x601)
MsrValue	= AsmReadMsr64 (MSR_PM_PBF_CMD);
PBF	MSR programming for interrupt/ratio limits
MSR_PM_WAY_0	(0xA01)	C-state way
MsrValue	= AsmReadMsr64 (MSR_PM_WAY_0);
PBF2	enable
if	*((UINT8* )((UINTN)mPpmContext + 299)) {**
Socket	type specific: SKX (0x5065) and variants
if	((UINT32 )(GetPpmInfoTable () + 72) == 0x5065		**
MSR_PPM_HWP_LIMIT	(0x1AA)
if	*(((UINT8* )((UINTN)mPpmContext + 150) & 4) != 0) {**
Package	power limit config
if	*((UINT32* )(GetPpmInfoTable () + 72) == 0x50655 &&**
PBF	core programming via MSR_PM_DISABLE (0x774)
if	*((UINT8* )((UINTN)mPpmContext + 223)) {**
PPM	Idle / C-State Initialization
MSR_PKG_CST_CONFIG_CONTROL	(0xE2)
MsrValue	= AsmReadMsr64 (MSR_PKG_CST_CONFIG_CONTROL);
Check	C1E and C-state limits
if	*((UINT8* )((UINTN)mPpmContext + 216) &&**
Check	IO MWAIT redirection
if	*((INT8* )((UINTN)mPpmContext + 4) < 0) {**
PPM	PBF MSR Configuration
Check	PPM_LIMIT_RATIOS
UINT64	MsrLimitRatios;
Clear	bit 20 and program from context
MsrLimitRatios	&= 0xFFEFFFFF;
Program	MSR_PPM_INTERRUPT and MSR_PPM_INTERRUPT2 with mask values
MsrInterrupt	= (UINT64 )((UINTN)mPpmContext + 265)	(MsrInterrupt & (UINT64 )((UINTN)mPpmContext + 273));**
PPM	Energy-Efficient Turbo / HWP Configuration
Check	for Package C-state limit type 3
if	*((UINT8* )((UINTN)mPpmContext + 212) == 3) {**
Package	power limit MSR_MSR_PKG_POWER_LIMIT if needed
if	*((UINT8* )((UINTN)mPpmContext + 215)) {**
PPM	Package Power Limit Configuration
This	area configures package power limit MSR registers.
In	the original binary, this is found in the SKX-specific
path	within PpmMsrConfig.
PPM	PMAX Offset Table Search
Read	CPU configuration context
ConfigContext	= (UINTN)GetPcdProtocol ()->GetPcd (PCD_TOKEN_PM_MODE);
Read	TDP and IccMax from PPM config registers
TdpValue	= ((UINT32)GetPcdProtocol ()->GetPcd (PCD_TOKEN_PPM_TDP) >> 3) & 7;
Use	table-based PMAX offset search
Result	= (UINT32)GetPcdProtocol ()->GetPcd (PCD_TOKEN_PPM_INFO);
Use	MSR-based TDP
UINT16	MsrTdp;
BIOS_RESET_CPL	Handshake
Read	current register value
RegValue	= GetPcdProtocol ()->GetPcd (PCD_TOKEN_PPM_INFO);
Set	CPL value based on phase
switch	(CplPhase) {
If	CplPhase is 0, set bit 0
if	(CplPhase == 0) {
Write	CPL value to register and record in boot script
GetPcdProtocol	()->GetPcd (PCD_TOKEN_PPM_INFO);
Poll	for PCU acknowledgement
PollCount	= 5;
SmmReadyToLock	Callback
Close	boot script table
BootScriptCloseTable	(NULL);
Free	boot script buffer
Free	boot script pool
VOID	*ScriptBuffer;
Internal	Helpers
CPUID	/ TSC / Intrinsics
Protocol	/ HOB / PCD Helpers
S3	Boot Script Helpers
Allocate	new buffer
EFI_STATUS	Status;
Register	SmmReadyToLock event for boot script save
mEventDxeSmmReadyToLock	*= (VOID )GetPcdProtocol ()->GetPcd (PCD_TOKEN_CPU_PM_REG_ADDR);**
In	the original binary, this writes the table length and
finalizes	the boot script entry list.
if	(mS3BootScriptInited) {
Close	the S3 boot script table
Get	current entry count
Index	*= 3 MsrIndex;**
Need	to expand the buffer
UINT64	NewCount;
Write	boot script entry
BufferEntry	*= (UINTN* )((UINTN )(ConfigContext + 40) + 8 * Index + 16);**
PPM	HOB Search
Memory	Copy Implementation (Used internally by boot script save)
Src	= &Src[Count - 1];
Copy	forward in 8-byte chunks then remainder
UINT64	Count8;
Assert	/ Print Handler
Read	CMOS 0x4B to get platform ID
IoWrite8	**(0x70, IoRead8 (0x70) & 0x80	0x4B);**
Determine	error level mapping based on platform ID
switch	(PlatformId) {
EFI_D_INFO	equivalent
Call	debug protocol if error level matches
if	(ErrorLevel != 0) {
Assert	Macro Implementation

Generated by HR650X BIOS Decompilation Project