/** @file
  SBDXE.h -- Header for SBDXE

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __SBDXE_H__
#define __SBDXE_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
GetPcdProtocol(
  VOID
);

EFI_STATUS
EFIAPI
SbdInstallPcieSegBusTable(
  VOID
);

EFI_STATUS
EFIAPI
SbdAssert(
  VOID
);

EFI_STATUS
EFIAPI
SbdDebugPrint(
  VOID
);

EFI_STATUS
EFIAPI
GetPciExpressBaseAddress(
  VOID
);

EFI_STATUS
EFIAPI
GetPchSku(
  VOID
);

EFI_STATUS
EFIAPI
GetPchStepping(
  VOID
);

EFI_STATUS
EFIAPI
XhciWrite32(
  VOID
);

EFI_STATUS
EFIAPI
XhciRead32(
  VOID
);

EFI_STATUS
EFIAPI
XhciDisablePort(
  VOID
);

EFI_STATUS
EFIAPI
UsbPerPortDisableCallback(
  VOID
);

EFI_STATUS
EFIAPI
SaveBootScriptToLockBox(
  VOID
);

EFI_STATUS
EFIAPI
SetBootScriptLockBoxAttributes(
  VOID
);

EFI_STATUS
EFIAPI
InitBootScriptTable(
  VOID
);

EFI_STATUS
EFIAPI
BootScriptReadyToLockNotify(
  VOID
);

EFI_STATUS
EFIAPI
BootScriptCloseNotify(
  VOID
);

EFI_STATUS
EFIAPI
CloseBootScriptTable(
  VOID
);

EFI_STATUS
EFIAPI
BootScriptContextCloseNotify(
  VOID
);

EFI_STATUS
EFIAPI
InitializeDxeServices(
  VOID
);

EFI_STATUS
EFIAPI
LocateSmmCommunicationProtocol(
  VOID
);

EFI_STATUS
EFIAPI
InitializeLibGlobals(
  VOID
);

EFI_STATUS
EFIAPI
SBDxeInitialize(
  VOID
);

EFI_STATUS
EFIAPI
SBDxeEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressRead32(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressWrite32(
  VOID
);

EFI_STATUS
EFIAPI
IoRead16(
  VOID
);

EFI_STATUS
EFIAPI
IoWrite16(
  VOID
);

EFI_STATUS
EFIAPI
IoRead32(
  VOID
);

EFI_STATUS
EFIAPI
IoWrite32(
  VOID
);

EFI_STATUS
EFIAPI
IoRead8(
  VOID
);

EFI_STATUS
EFIAPI
IoWrite8(
  VOID
);

EFI_STATUS
EFIAPI
MemZero(
  VOID
);

EFI_STATUS
EFIAPI
Data(
  VOID
);

EFI_STATUS
EFIAPI
gImageHandle       = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
list pointer (from DXE HOB library)(
  VOID
);

EFI_STATUS
EFIAPI
*gHobList  = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
(MM PCI base) from DxeMmPciBaseLib(
  VOID
);

EFI_STATUS
EFIAPI
*gPciUsra  = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
Base Address (from PCD)(
  VOID
);

EFI_STATUS
EFIAPI
gPciExpressBaseAddr = 0;(
  VOID
);

EFI_STATUS
EFIAPI
stepping / SKU global state(
  VOID
);

EFI_STATUS
EFIAPI
gPchStepping = 3;    ///< Initial state; determined at first call(
  VOID
);

EFI_STATUS
EFIAPI
Script / S3 state(
  VOID
);

EFI_STATUS
EFIAPI
gBootScriptTable     = 0;(
  VOID
);

EFI_STATUS
EFIAPI
USB port disable state: set to TRUE after first callback(
  VOID
);

EFI_STATUS
EFIAPI
gXhciPortDisableDone = FALSE;(
  VOID
);

EFI_STATUS
EFIAPI
protocol, SMM Communication protocol(
  VOID
);

EFI_STATUS
EFIAPI
*gPcdProtocol         = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
via SMM PCI base protocol(
  VOID
);

EFI_STATUS
EFIAPI
VOID  *mPciUsra = NULL;(
  VOID
);

EFI_STATUS
EFIAPI
Definitions(
  VOID
);

EFI_STATUS
EFIAPI
gPchRcConfigGuid            = { 0x6350F689, 0x6EF9, 0x4B9A, { 0x87, 0xA0, 0xBB, 0xF6, 0x4D, 0x35, 0x08, 0xED }};(
  VOID
);

EFI_STATUS
EFIAPI
for PiSmmCommunicationRegionTable (for SMM LockBox)(
  VOID
);

EFI_STATUS
EFIAPI
gSmmCommRegionGuid          = { 0x8E7BE0F9, 0x3D41, 0x42D9, { 0x9F, 0xFF, 0xAC, 0xC0, 0x88, 0xC2, 0xC8, 0x32 }};(
  VOID
);

EFI_STATUS
EFIAPI
Prototypes (local)(
  VOID
);

EFI_STATUS
EFIAPI
EFI_STATUS(
  VOID
);

EFI_STATUS
EFIAPI
helper: ASSERT macro with message(
  VOID
);

EFI_STATUS
EFIAPI
SKU Detection(
  VOID
);

EFI_STATUS
EFIAPI
LPC/eSPI device ID from PCI config space (Bus 0, Dev 31, Func 0, offset 2)(
  VOID
);

EFI_STATUS
EFIAPI
= IoRead16 (PCI_EXPRESS_LIB_ADDRESS (0, 31, 0, 0x02));(
  VOID
);

EFI_STATUS
EFIAPI
if device ID falls in the PCH-H range(
  VOID
);

EFI_STATUS
EFIAPI
(((LpcDevId + 24128) & 0xFF70) == 0) {(
  VOID
);

EFI_STATUS
EFIAPI
is PCH-H (SKU 1)(
  VOID
);

EFI_STATUS
EFIAPI
= 1;(
  VOID
);

EFI_STATUS
EFIAPI
is PCH-LP (SKU 2)(
  VOID
);

EFI_STATUS
EFIAPI
= 2;(
  VOID
);

EFI_STATUS
EFIAPI
Stepping Detection(
  VOID
);

EFI_STATUS
EFIAPI
the PCH RID (Revision ID) from PCI config(
  VOID
);

EFI_STATUS
EFIAPI
the base address for PCH info from the PchInfoLib(
  VOID
);

EFI_STATUS
EFIAPI
= PciExpressRead32 ((
  VOID
);

EFI_STATUS
EFIAPI
the LPC device ID for stepping decode(
  VOID
);

EFI_STATUS
EFIAPI
stepping based on Device ID + Rev ID(
  VOID
);

EFI_STATUS
EFIAPI
(((LpcDeviceId + 24128) & 0xFF70) == 0) {(
  VOID
);

EFI_STATUS
EFIAPI
(RevId) {(
  VOID
);

EFI_STATUS
EFIAPI
case 0x10:(
  VOID
);

EFI_STATUS
EFIAPI
case 0x20:(
  VOID
);

EFI_STATUS
EFIAPI
case 0x30:(
  VOID
);

EFI_STATUS
EFIAPI
case 0x31:(
  VOID
);

EFI_STATUS
EFIAPI
default:(
  VOID
);

EFI_STATUS
EFIAPI
((UINT16)(LpcDeviceId + 25280) <= 8) {(
  VOID
);

EFI_STATUS
EFIAPI
/ LP D0(
  VOID
);

EFI_STATUS
EFIAPI
/ LP D1(
  VOID
);

EFI_STATUS
EFIAPI
/ LP D2(
  VOID
);

EFI_STATUS
EFIAPI
/ LP D3(
  VOID
);

EFI_STATUS
EFIAPI
none of the above, check for D/E stepping(
  VOID
);

EFI_STATUS
EFIAPI
(((LpcDeviceId + 24128) & 0xFF70) != 0) {(
  VOID
);

EFI_STATUS
EFIAPI
the RTC CMOS register for stepping hints(
  VOID
);

EFI_STATUS
EFIAPI
} else if (RevId == 2) {(
  VOID
);

EFI_STATUS
EFIAPI
} else if (RevId == 3) {(
  VOID
);

EFI_STATUS
EFIAPI
} else if (RevId == 4) {(
  VOID
);

EFI_STATUS
EFIAPI
} else if (RevId == 5) {(
  VOID
);

EFI_STATUS
EFIAPI
} else if (RevId == 6) {(
  VOID
);

EFI_STATUS
EFIAPI
} else {(
  VOID
);

EFI_STATUS
EFIAPI
}(
  VOID
);

EFI_STATUS
EFIAPI
Per-Port Disable Logic(
  VOID
);

EFI_STATUS
EFIAPI
is already disabled, nothing to do.(
  VOID
);

EFI_STATUS
EFIAPI
port disable(
  VOID
);

EFI_STATUS
EFIAPI
(IsSSPort) {(
  VOID
);

EFI_STATUS
EFIAPI
SS ports, set Port Disable + Reset(
  VOID
);

EFI_STATUS
EFIAPI
(XhciBar, PortBase, 0x8000FE00);(
  VOID
);

EFI_STATUS
EFIAPI
up to 3 seconds (3000 * 1ms)(
  VOID
);

EFI_STATUS
EFIAPI
(Timeout = 0; Timeout < 3000; Timeout++) {(
  VOID
);

EFI_STATUS
EFIAPI
HS ports, set Port Reset + Port Disable(
  VOID
);

EFI_STATUS
EFIAPI
(XhciBar, PortBase, 0x210);(
  VOID
);

EFI_STATUS
EFIAPI
up to 200ms (200 * 1ms)(
  VOID
);

EFI_STATUS
EFIAPI
(Timeout = 0; Timeout < 200; Timeout++) {(
  VOID
);

EFI_STATUS
EFIAPI
PCH SKU for port count and register layout(
  VOID
);

EFI_STATUS
EFIAPI
= GetPchSku ();(
  VOID
);

EFI_STATUS
EFIAPI
PchRcConfiguration variable from runtime services(
  VOID
);

EFI_STATUS
EFIAPI
= sizeof (PortConfig);(
  VOID
);

EFI_STATUS
EFIAPI
XHCI BAR(
  VOID
);

EFI_STATUS
EFIAPI
= 0xA0010;  // EFI_PCI_IO_ATTRIBUTE_MEMORY(
  VOID
);

EFI_STATUS
EFIAPI
= PciExpressRead32 (PCI_EXPRESS_LIB_ADDRESS (0, 20, 0, 0x10));(
  VOID
);

EFI_STATUS
EFIAPI
64-bit BAR if needed(
  VOID
);

EFI_STATUS
EFIAPI
((PciExpressRead32 (PCI_EXPRESS_LIB_ADDRESS (0, 20, 0, 0x10)) & 0x06) == 0x04) {(
  VOID
);

EFI_STATUS
EFIAPI
current HS PDO, SS PDO, and SSPE values(
  VOID
);

EFI_STATUS
EFIAPI
= XhciRead32 (XhciBar, XHCI_HSPDO_OFS);(
  VOID
);

EFI_STATUS
EFIAPI
HS (USB 2.0) ports(
  VOID
);

EFI_STATUS
EFIAPI
(PortIndex = 0; PortIndex < MaxHsPorts; PortIndex++) {(
  VOID
);

EFI_STATUS
EFIAPI
wants port disabled(
  VOID
);

EFI_STATUS
EFIAPI
&= ~DisableMask;(
  VOID
);

EFI_STATUS
EFIAPI
wants port enabled(
  VOID
);

EFI_STATUS
EFIAPI
|= DisableMask;(
  VOID
);

EFI_STATUS
EFIAPI
SS (USB 3.0) ports(
  VOID
);

EFI_STATUS
EFIAPI
(PortIndex = 0; PortIndex < MaxSsPorts; PortIndex++) {(
  VOID
);

EFI_STATUS
EFIAPI
SSPE value(
  VOID
);

EFI_STATUS
EFIAPI
(PortConfig[1254] != 0) {(
  VOID
);

EFI_STATUS
EFIAPI
SS ports explicitly managed(
  VOID
);

EFI_STATUS
EFIAPI
(Sku == 2) {(
  VOID
);

EFI_STATUS
EFIAPI
SSPE from SS PDO(
  VOID
);

EFI_STATUS
EFIAPI
= SsPdo;(
  VOID
);

EFI_STATUS
EFIAPI
back the PDO and SSPE registers(
  VOID
);

EFI_STATUS
EFIAPI
((DEBUG_INFO, "Write back Xhci HS PDO value: %x to HS PDO register\n", HsPdo));(
  VOID
);

EFI_STATUS
EFIAPI
physically disable each port that was marked for disable(
  VOID
);

EFI_STATUS
EFIAPI
HS port needs to be disabled(
  VOID
);

EFI_STATUS
EFIAPI
(PortIndex < 12) {(
  VOID
);

EFI_STATUS
EFIAPI
SS port needs to be disabled(
  VOID
);

EFI_STATUS
EFIAPI
Script Support(
  VOID
);

EFI_STATUS
EFIAPI
SMM communication buffer for LockBox save(
  VOID
);

EFI_STATUS
EFIAPI
= &LocalBuffer[0];(
  VOID
);

EFI_STATUS
EFIAPI
the LockBox communication buffer:(
  VOID
);

EFI_STATUS
EFIAPI
(BufferPtr, &gBootScriptContextGuid, sizeof (EFI_GUID));(
  VOID
);

EFI_STATUS
EFIAPI
*((UINT64 *)&BufferPtr[24]) = (UINT64)-1;(
  VOID
);

EFI_STATUS
EFIAPI
*((UINT32 *)&BufferPtr[36]) = 48;    // Header size(
  VOID
);

EFI_STATUS
EFIAPI
LockBox communication buffer for SetAttributes command(
  VOID
);

EFI_STATUS
EFIAPI
version(
  VOID
);

EFI_STATUS
EFIAPI
size(
  VOID
);

EFI_STATUS
EFIAPI
CommSize = 64;(
  VOID
);

EFI_STATUS
EFIAPI
Boot Script Initialization(
  VOID
);

EFI_STATUS
EFIAPI
runtime memory page for the boot script table(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, 1, &PcdValue);(
  VOID
);

EFI_STATUS
EFIAPI
the PCD value for the boot script table address(
  VOID
);

EFI_STATUS
EFIAPI
(PcdBootScriptTableAddress, PcdValue);(
  VOID
);

EFI_STATUS
EFIAPI
that the boot script table is ready(
  VOID
);

EFI_STATUS
EFIAPI
= PcdValue;(
  VOID
);

EFI_STATUS
EFIAPI
notification for DxeSmmReadyToLock(
  VOID
);

EFI_STATUS
EFIAPI
((
  VOID
);

EFI_STATUS
EFIAPI
event notification(
  VOID
);

EFI_STATUS
EFIAPI
the boot script table(
  VOID
);

EFI_STATUS
EFIAPI
the current boot script data to LockBox(
  VOID
);

EFI_STATUS
EFIAPI
LockBox attributes(
  VOID
);

EFI_STATUS
EFIAPI
();(
  VOID
);

EFI_STATUS
EFIAPI
for subsequent boot script close events(
  VOID
);

EFI_STATUS
EFIAPI
(gSmmCommunicationProtocol != NULL) {(
  VOID
);

EFI_STATUS
EFIAPI
close event callbacks for S3 resume paths(
  VOID
);

EFI_STATUS
EFIAPI
cleanup callbacks(
  VOID
);

EFI_STATUS
EFIAPI
the new table to the LockBox(
  VOID
);

EFI_STATUS
EFIAPI
the PCD to the locked value(
  VOID
);

EFI_STATUS
EFIAPI
(PcdBootScriptTableAddress, gBootScriptTable);(
  VOID
);

EFI_STATUS
EFIAPI
Segment Bus Table Setup(
  VOID
);

EFI_STATUS
EFIAPI
the number of PCIe segments from PCD(
  VOID
);

EFI_STATUS
EFIAPI
= GetPcdProtocolPtr ();(
  VOID
);

EFI_STATUS
EFIAPI
and initialize the bus table(
  VOID
);

EFI_STATUS
EFIAPI
= AllocateZeroPool (NumSegments);(
  VOID
);

EFI_STATUS
EFIAPI
the PCH-specific installation routine(
  VOID
);

EFI_STATUS
EFIAPI
config base(
  VOID
);

EFI_STATUS
EFIAPI
Express Base Address Initialization(
  VOID
);

EFI_STATUS
EFIAPI
Service Table and HOB List Discovery(
  VOID
);

EFI_STATUS
EFIAPI
Communication Protocol Discovery(
  VOID
);

EFI_STATUS
EFIAPI
Constructor-Style Init(
  VOID
);

EFI_STATUS
EFIAPI
UEFI core services(
  VOID
);

EFI_STATUS
EFIAPI
= ImageHandle;(
  VOID
);

EFI_STATUS
EFIAPI
DXE services table and HOB list from configuration table(
  VOID
);

EFI_STATUS
EFIAPI
Driver Initialization(
  VOID
);

EFI_STATUS
EFIAPI
(ImageHandle, SystemTable);(
  VOID
);

EFI_STATUS
EFIAPI
driver uses the simpler callback registration model.(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->LocateProtocol ((
  VOID
);

EFI_STATUS
EFIAPI
protocol may not be available yet; we try again in callbacks.(
  VOID
);

EFI_STATUS
EFIAPI
= NULL;(
  VOID
);

EFI_STATUS
EFIAPI
= GetPchStepping ();(
  VOID
);

EFI_STATUS
EFIAPI
used to enable write-combining for PCIe MMIO range(
  VOID
);

EFI_STATUS
EFIAPI
PCIe ECAM (enhanced configuration access mechanism)(
  VOID
);

EFI_STATUS
EFIAPI
(PcdGet16 (PcdPciExpressBaseAddress), 0x500);(
  VOID
);

EFI_STATUS
EFIAPI
= (GetPchSku () == 2);(
  VOID
);

EFI_STATUS
EFIAPI
(((TimeoutValue + 357 - IoRead32 (PcdGet16 (PcdAcpiBaseAddress))) & 0x800000) == 0) {(
  VOID
);

EFI_STATUS
EFIAPI
(IsPchLp) {(
  VOID
);

EFI_STATUS
EFIAPI
= InitBootScriptTable (&gBootScriptTable);(
  VOID
);

EFI_STATUS
EFIAPI
= gBS->CreateEvent ((
  VOID
);

EFI_STATUS
EFIAPI
Entry Point(
  VOID
);

EFI_STATUS
EFIAPI
the main initialization routine(
  VOID
);

EFI_STATUS
EFIAPI
= SBDxeInitialize (ImageHandle, SystemTable);(
  VOID
);

EFI_STATUS
EFIAPI
/ Debug Helpers(
  VOID
);

EFI_STATUS
EFIAPI
Express MMIO Read/Write Helpers (used for chipset access)(
  VOID
);

EFI_STATUS
EFIAPI
Port Helpers(
  VOID
);

EFI_STATUS
EFIAPI
aligned copy for speed when possible.(
  VOID
);

EFI_STATUS
EFIAPI
back to byte copy for tail bytes.(
  VOID
);

EFI_STATUS
EFIAPI
((Src < Dest) && ((UINT8 *)Src + Count - 1 >= (UINT8 *)Dest)) {(
  VOID
);

EFI_STATUS
EFIAPI
(Dest, Src, Count);(
  VOID
);

#endif /* __SBDXE_H__ */