| Address | Name | Description |
|---|---|---|
| SmbiosBoardEntryPoint | ||
| GetConfigTable | ||
| IoRead32 | ||
| GetBoardType | ||
| WriteBoardConfig | ||
| GetPciExpressBaseAddress | ||
| LocateMmPciBaseProtocol | ||
| UnsupportedStub | ||
| MmPciAccess | ||
| DestructorDispatch | ||
| DebugAssert | ||
| ReadUnaligned64 | ||
| CompareGuid | ||
| NullCallback | ||
| ReadTsc | ||
| ReadCallerEflags | ||
| CpuPause | ||
| EnableInterrupts | ||
| DisableInterrupts | ||
| SmbiosBoard | Protocol GUID: | |
| EFI_GUID | gSmbiosBoardProtocolGuid = SMBIOS_BOARD_PROTOCOL_GUID; | |
| EFI_GUID | gMmPciBaseProtocolGuid = MMPCI_BASE_PROTOCOL_GUID; | |
| Library | instance globals (populated at entry) | |
| EFI_HANDLE | gImageHandle = NULL; | |
| SmbiosBoard | Protocol instance. | |
| Contains | board data and function dispatch table installed at entry. | |
| STATIC | SMBIOS_BOARD_PROTOCOL mSmbiosBoardProtocol = { | |
| BoardData | - board type and identification bytes | |
| Reserved | // | |
| LocateMmPci | - LocateMmPciBaseProtocol | |
| Destructor | callback table (terminated by NULL entry) | |
| STATIC | VOID (*mDestructorTable[])(VOID) = { | |
| Initialize | library globals | |
| gImageHandle | = ImageHandle; | |
| Locate | DxeServicesTable from configuration table | |
| Status | = GetConfigTable (&gEfiDxeServicesTableGuid, (VOID )&gDS);** | |
| Locate | MmPciBase protocol for PCI configuration space access | |
| if | (mPciUsra == NULL) { | |
| Initialize | HOB list | |
| GetHobList | (); | |
| Get | PCD protocol for PCIe configuration | |
| PcdProtocol | = GetPcdProtocol (); | |
| Read | PCI Express base address from PCD token 5 | |
| mPciExpressBaseAddress | = PcdProtocol->Get64 (5); | |
| Get | PCIe segment/bus table size from PCD token 7 | |
| PciSegBusTableSize | = (UINT64)PcdProtocol->Get64 (7); | |
| Copy | PCIe segment/bus table to static buffer | |
| CopyMem | ((VOID *)(UINTN)&mSmbiosBoardProtocol.PcdSizeConstant | |
| Write | board configuration flag to PCI config space | |
| if | (GetPciExpressBaseAddress () >= 0) { | |
| Read | board type from CMOS/RTC | |
| Eflags | = ReadCallerEflags (); | |
| Timed | spin-wait loop: wait ~2 seconds (33554432 * TSC ticks) | |
| TscStart | = ReadTsc (); | |
| Restore | interrupt state | |
| if | (InterruptsWereEnabled) { | |
| Install | SmbiosBoard protocol | |
| Read | CMOS register 0x4B | |
| Preserve | NMI mask (bit 7) in index register 0x70 | |
| CmosIndex | = __inbyte (0x70); | |
| CMOS | battery may be dead; read chipset straps from | |
| BoardIdAdjusted | *= ((volatile UINT8 *)(UINTN)0xFDAF0490) & 2 | 1;** |
| Token | 1024064 / 1024068 corresponds to the PCIe base address PCD | |
| if | (Address & ~0xFFFFFFF) { | |
| In | UEFI, the address validation is for addresses with bits beyond | |
| the | 28-bit PCIe MMIO window | the ASSERT below would fire |
| The | protocol's entry at offset 0x20 (index 4 into vtable) | |
| is | expected to be a function with: | |
| For | this driver, Operation=4, with a result buffer. | |
| Result | = 1; | |
| Locate | StatusCode Runtime Protocol for debug output | |
| Status | = gBS->LocateProtocol ( | |
| Report | status code with the assertion message | |
| Src | = &Src[Length - 1]; | |
| Copy | remainder byte-by-byte (backwards) | |
| for | ( ; Length != 0; Length--) { | |
| No | overlap or Source after Destination: copy forwards | |
| Count | = Length; | |
| Copy | remaining bytes |
Generated by HR650X BIOS Decompilation Project