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Ajax Dong
Volume_Top_File
Function Table
| Address | Name | Description | |
|---|---|---|---|
| ModuleEntryPointThunk | |||
| SecHandleSysCalls | |||
| SecStartup | |||
| SecCoreEntryPoint | |||
| InstallSecPpi | |||
| FindPeiCore | |||
| PeiCoreEntryPoint | |||
| SecBist | |||
| SecTemporaryRamSupport | |||
| PeiServiceLocatePpi | |||
| SecInitializeBootMode | |||
| SecInitializeFpu | |||
| SecReadSecCoreData | |||
| SecSetupGdt | |||
| SecSetupExceptionHandlers | |||
| SecExceptionDispatcher | |||
| NullExceptionHandler | |||
| NullFunction | |||
| ExceptionHandler0 | |||
| ExceptionHandler1 | |||
| ExceptionHandler3 | |||
| ExceptionHandler4 | |||
| ExceptionHandler5 | |||
| ExceptionHandler6 | |||
| PeCoffGetEntryPoint | |||
| Assert | |||
| SerialPortWrite | |||
| SecWriteCr0 | |||
| SecWriteCr4 | |||
| SecEnableSse | |||
| SecSwitchStack | |||
| SecReadIdtBase | |||
| SecInitIdtEntry | |||
| WriteMsr | |||
| LidtWrapper | |||
| SidtWrapper | |||
| IoWrite32 | |||
| IoRead16 | |||
| IoReadWrite8 | |||
| PciCfgReadWrite | |||
| Transition | stub - handles call from _ModuleEntryPoint | ||
| System | call handling placeholder | ||
| Read | boot mode from CMOS | ||
| Initialize | FPU | ||
| Copy | default IDT entry template from .data section | ||
| Save | current IDTR | ||
| Calculate | how many IDT entries we need (max 32) | ||
| Initialize | IDT entries with exception gate type 0x8E | ||
| CS | segment selector | ||
| Build | SecCoreData structure | ||
| Number | of fields in SecCoreData | ||
| Find | PEI Core entry point | ||
| Hang | } | ||
| Check | for PPI descriptors (NullStub returns 0 if none) | ||
| Copy | PPIs - first descriptor at Dst (24 bytes) | ||
| Copy | remaining descriptors from PEI Core | ||
| Update | PEI temporary RAM usage | ||
| Empty | PPI descriptor | ||
| IF | flag | ||
| Walk | through FFS files in the firmware volume | ||
| Handle | extended FFS header | ||
| EFI_NOT_FOUND | } else { | ||
| Check | file type: PEIM (3) or FV_PEIM (4) | ||
| Walk | sections within this PEIM file | ||
| Extended | header | ||
| PE32 | section (16) or TE section (18) | ||
| Found | both PE32 and TE entry points | ||
| Find | PEI Core in FV | ||
| Zero | the buffer and relocate PE32 image | ||
| Relocate | TE image | ||
| Get | entry point from PEI Core | ||
| Try | to locate primary BIST PPI | ||
| EFI_NOT_FOUND | Result = PeiServiceLocatePpi(PeiServicesTablePointer | ||
| Invalidate | cache | ||
| Save | and disable MTRR_DEF_TYPE | ||
| Clear | MTRR_PHYS_BASE_0 valid bit and set type | ||
| Restore | MTRR_DEF_TYPE | ||
| exception type and APIC ID | |||
| Exception | data (for page faults etc) | ||
| Page | fault | ||
| Dump | all CPU registers | ||
| Read | the current temporary RAM stack pointer | ||
| Register | PPI notification | ||
| EFI_NOT_FOUND | return -2147483634; | ||
| EFI_INVALID_PARAMETER | // Wait for callback | ||
| Limit | + Base | ||
| Read | CMOS byte at index 0x6C | ||
| CMOS | index | ||
| Dummy | read | ||
| CMOS | boot mode byte | ||
| Read | boot mode value | ||
| Decode | baud rate | ||
| 115200 | / BaudRate | ||
| Initialize | serial port if one is detected | ||
| Only | set if divisor value changed or line control not 3 | ||
| Wait | for transmitter ready | ||
| Set | divisor latch and baud rate | ||
| 8N1 | __outbyte(SerialPort + 2, 0); // FIFO off | ||
| FIFO | on | ||
| Default | FPU control word initialization | ||
| Platform | with IOH (3 config entries) | ||
| Platform | with PCH (2 config entries) | ||
| Setup | GDT and exception handlers for 6 entries (18 bytes / 3) | ||
| Enter | configuration mode | ||
| Write | GDT entry base (4 bytes) | ||
| Read | current limit+flags, set to 2 (32-bit) | ||
| Flush | configuration | ||
| Read | back the 4-byte GDT value | ||
| Write | handler address (4 bytes at 0xF0-0xF3) | ||
| Write | gate type & segment (4 bytes at 0xF4-0xF7) | ||
| Set | gate type = interrupt gate (bit 1 of byte 5) | ||
| Set | segment selector = 0x08 (CS) at register FE | ||
| Direct | write | ||
| IOH | error configuration | ||
| IOH | PCI configuration for error logging | ||
| IRET | - return from exception | ||
| Returns | entry point address within the relocated image | ||
| IA32 | **Machine == 0x200 | // IA64** | |
| ARM7 | ? | ||
| X64 | Machine == 0xAA64) // AARCH64 | ||
| ARM | return WordPtr; | ||
| Read | debug level from CMOS | ||
| Disabled | if (!DebugLevel) | ||
| All | debug disabled | ||
| Format | and push to serial | ||
| Poll | for transmitter ready (bit 6) | ||
| Wait | for THR empty (bit 5) | ||
| Write | up to 16 bytes | ||
| different | IIO stacks (0-3) and PCI segments. | ||
| Sets | values via IoRead32/IoWrite32 to 0xF8080/0xF8082. | ||
| Read | existing config from 0xF8080, modify, write back | ||
| Also | mirror to MSRs 0xFDEF2770/0xFDEF2774 | ||
| Walk | HOB chain looking for matching type | ||
| Allocate | HOB with GUID header + data | ||
| Handles | width, precision, padding, type conversion | ||
| Remaining | functions follow standard UEFI library implementations: | ||
| See | Volume_Top_File.md for complete function list. |
Generated by HR650X BIOS Decompilation Project