/** @file
TcgDxeplatform.h -- Header for TcgDxeplatform
Copyright (c) HR650X BIOS Decompilation Project
**/
#ifndef __TCGDXEPLATFORM_H__
#define __TCGDXEPLATFORM_H__
#include "../uefi_headers/Uefi.h"
//
// Function Prototypes
//
EFI_STATUS
EFIAPI
ReadUnaligned64(
VOID
);
EFI_STATUS
EFIAPI
IoRead32(
VOID
);
EFI_STATUS
EFIAPI
AssertReport(
VOID
);
EFI_STATUS
EFIAPI
ReportStatusCode(
VOID
);
EFI_STATUS
EFIAPI
PciExpressReadAddress(
VOID
);
EFI_STATUS
EFIAPI
PciWriteWord(
VOID
);
EFI_STATUS
EFIAPI
CompareGuid(
VOID
);
EFI_STATUS
EFIAPI
GetNextGuidHob(
VOID
);
EFI_STATUS
EFIAPI
TcgDxePlatformInit(
VOID
);
EFI_STATUS
EFIAPI
TcgDxePlatformDispatch(
VOID
);
EFI_STATUS
EFIAPI
TcgDxePlatformEntryPoint(
VOID
);
EFI_STATUS
EFIAPI
variables(
VOID
);
EFI_STATUS
EFIAPI
gImageHandle = NULL;(
VOID
);
EFI_STATUS
EFIAPI
used for HOB search (TCG platform protocol HOB GUID)(
VOID
);
EFI_STATUS
EFIAPI
CONST GUID mTcgPlatformHobGuid = TCG_PLATFORM_HOB_GUID;(
VOID
);
EFI_STATUS
EFIAPI
used for LocateProtocol (TCG platform protocol GUID)(
VOID
);
EFI_STATUS
EFIAPI
CONST GUID mTcgPlatformProtocolGuid = TCG_PLATFORM_PROTOCOL_GUID;(
VOID
);
EFI_STATUS
EFIAPI
CONST GUID mEfiDxeServicesTableGuid = EFI_DXE_SERVICES_TABLE_GUID;(
VOID
);
EFI_STATUS
EFIAPI
if we have more than 16 bytes of memory per index 31;(
VOID
);
EFI_STATUS
EFIAPI
so, this is likely an SMM environment and we should not(
VOID
);
EFI_STATUS
EFIAPI
to locate the protocol.(
VOID
);
EFI_STATUS
EFIAPI
(IoRead32 (31) > 0x10) {(
VOID
);
EFI_STATUS
EFIAPI
CMOS index 0x4B to determine platform type.(
VOID
);
EFI_STATUS
EFIAPI
register provides the platform type identifier.(
VOID
);
EFI_STATUS
EFIAPI
(0x70, (IoRead8 (0x70) & 0x80) | 0x4B);(
VOID
);
EFI_STATUS
EFIAPI
platform type mask(
VOID
);
EFI_STATUS
EFIAPI
= 0;(
VOID
);
EFI_STATUS
EFIAPI
type 0 has special handling; check a hardware register(
VOID
);
EFI_STATUS
EFIAPI
0xFEDAF0490 for the actual type.(
VOID
);
EFI_STATUS
EFIAPI
(PlatformType == 0) {(
VOID
);
EFI_STATUS
EFIAPI
platform type; determine the mask.(
VOID
);
EFI_STATUS
EFIAPI
(PlatformType == 1) {(
VOID
);
EFI_STATUS
EFIAPI
4 or other(
VOID
);
EFI_STATUS
EFIAPI
through sub-HOBs within the current HOB entry, following(
VOID
);
EFI_STATUS
EFIAPI
length field at offset +2 (in UINT16 units).(
VOID
);
EFI_STATUS
EFIAPI
(*HobEnd != 0xFFFF && *HobEnd != 0x0004) {(
VOID
);
EFI_STATUS
EFIAPI
end of sub-HOBs, wrap back to the HOB start.(
VOID
);
EFI_STATUS
EFIAPI
(*HobEnd == 0xFFFF) {(
VOID
);
EFI_STATUS
EFIAPI
if the sub-HOB is a GUID Extension HOB (type 4)(
VOID
);
EFI_STATUS
EFIAPI
GUID matches our target HOB GUID.(
VOID
);
EFI_STATUS
EFIAPI
((*HobEnd == 0x0004) &&(
VOID
);
EFI_STATUS
EFIAPI
it; resource data starts at offset 12 (past the 16-byte GUID).(
VOID
);
EFI_STATUS
EFIAPI
to the next HOB.(
VOID
);
EFI_STATUS
EFIAPI
list must be present in DXE phase.(
VOID
);
EFI_STATUS
EFIAPI
(mHobList != NULL);(
VOID
);
EFI_STATUS
EFIAPI
global service table pointers and assert they are valid.(
VOID
);
EFI_STATUS
EFIAPI
= ImageHandle;(
VOID
);
EFI_STATUS
EFIAPI
the HOB list from the system configuration table.(
VOID
);
EFI_STATUS
EFIAPI
();(
VOID
);
EFI_STATUS
EFIAPI
the PCD protocol and read the PCI Express base address.(
VOID
);
EFI_STATUS
EFIAPI
= GetPcdProtocol ()->GetPcd (5);(
VOID
);
EFI_STATUS
EFIAPI
the PCI Express capability register at offset PCI_EXPRESS_CAP_REG_OFFSET.(
VOID
);
EFI_STATUS
EFIAPI
bit 7 is set (PCI Express capability present), write 0x500 to the register.(
VOID
);
EFI_STATUS
EFIAPI
((*(volatile INT8 *)PciExpressReadAddress (PCI_EXPRESS_CAP_REG_OFFSET) & 0x80) != 0) {(
VOID
);
EFI_STATUS
EFIAPI
0x500 to the capability register at offset PCI_EXPRESS_CAP_REG_OFFSET.(
VOID
);
EFI_STATUS
EFIAPI
((UINT16 *)PciExpressReadAddress (PCI_EXPRESS_CAP_REG_OFFSET));(
VOID
);
EFI_STATUS
EFIAPI
the enable bit (bit 7) at the same address.(
VOID
);
EFI_STATUS
EFIAPI
and then disable interrupts during the stabilization delay.(
VOID
);
EFI_STATUS
EFIAPI
= (AsmReadEflags () & EFI_FLAGS_IF) != 0;(
VOID
);
EFI_STATUS
EFIAPI
the initial TSC value and the delay timer from I/O port 0x508.(
VOID
);
EFI_STATUS
EFIAPI
= IoRead32 (TSC_DELAY_PORT) & 0xFFFFFF;(
VOID
);
EFI_STATUS
EFIAPI
lower 24 bits of (TscDelayValue + 357 - port 0x508) are checked;(
VOID
);
EFI_STATUS
EFIAPI
bit 23 becomes set, the delay is complete.(
VOID
);
EFI_STATUS
EFIAPI
(((TscDelayValue + TSC_DELAY_CONSTANT - IoRead32 (TSC_DELAY_PORT)) & TSC_DELAY_MASK) == 0) {(
VOID
);
EFI_STATUS
EFIAPI
the interrupt flag state.(
VOID
);
EFI_STATUS
EFIAPI
(InterruptsEnabled) {(
VOID
);
EFI_STATUS
EFIAPI
the system configuration table backwards, searching for(
VOID
);
EFI_STATUS
EFIAPI
DXE Services Table GUID.(
VOID
);
EFI_STATUS
EFIAPI
= gST->NumberOfTableEntries;(
VOID
);
EFI_STATUS
EFIAPI
entry GUID against gEfiDxeServicesTableGuid.(
VOID
);
EFI_STATUS
EFIAPI
(CompareMemWrapper (&Entry->VendorGuid, &mEfiDxeServicesTableGuid, sizeof (GUID)) == 0) {(
VOID
);
EFI_STATUS
EFIAPI
the DXE Services Table. The vendor table pointer contains(
VOID
);
EFI_STATUS
EFIAPI
HOB list. Extract the TCG platform protocol pointer from it.(
VOID
);
EFI_STATUS
EFIAPI
= Entry->VendorTable;(
VOID
);
EFI_STATUS
EFIAPI
the TCG platform protocol via LocateProtocol.(
VOID
);
EFI_STATUS
EFIAPI
= gBS->LocateProtocol ((
VOID
);
EFI_STATUS
EFIAPI
we have a HOB-derived protocol interface with revision 1(
VOID
);
EFI_STATUS
EFIAPI
the Initialize notification first.(
VOID
);
EFI_STATUS
EFIAPI
((HobData != NULL) && (*(UINT8 *)HobData == 1)) {(
VOID
);
EFI_STATUS
EFIAPI
the four TCG callbacks through the protocol.(
VOID
);
EFI_STATUS
EFIAPI
(!EFI_ERROR (Status)) {(
VOID
);
EFI_STATUS
EFIAPI
(TcgPlatformProtocol->ProcessPpiRequest () < 0) {(
VOID
);
EFI_STATUS
EFIAPI
(TcgPlatformProtocol->ProcessTcgSetup () < 0) {(
VOID
);
EFI_STATUS
EFIAPI
(TcgPlatformProtocol->MeasurePciOptionRoms () < 0) {(
VOID
);
EFI_STATUS
EFIAPI
= TcgPlatformProtocol->ReadyToBootCallback ();(
VOID
);
#endif /* __TCGDXEPLATFORM_H__ */