/** @file
  PchInitDxe.h -- Header for PchInitDxe

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __PCHINITDXE_H__
#define __PCHINITDXE_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
PchInitDxeEntry(
  VOID
);

EFI_STATUS
EFIAPI
PchInitEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
PchInitGlobalDataInit(
  VOID
);

EFI_STATUS
EFIAPI
PchInitS3BootScriptInit(
  VOID
);

EFI_STATUS
EFIAPI
PchS3BootScriptDeinit(
  VOID
);

EFI_STATUS
EFIAPI
PchInitS3BootScriptSave(
  VOID
);

EFI_STATUS
EFIAPI
PchRevealTraceHub(
  VOID
);

EFI_STATUS
EFIAPI
PchUplinksInit(
  VOID
);

EFI_STATUS
EFIAPI
InitializePchDevice(
  VOID
);

EFI_STATUS
EFIAPI
PchUsbPrecondition(
  VOID
);

EFI_STATUS
EFIAPI
PchUsbPreconditionTimerCallback(
  VOID
);

EFI_STATUS
EFIAPI
ConfigurePmForRstRemapping(
  VOID
);

EFI_STATUS
EFIAPI
PchPcieRpEarlyConfig(
  VOID
);

EFI_STATUS
EFIAPI
PchConfigureRpfnMapping(
  VOID
);

EFI_STATUS
EFIAPI
PchOnEndOfDxe(
  VOID
);

EFI_STATUS
EFIAPI
PchOnEndOfDxeWrapper(
  VOID
);

EFI_STATUS
EFIAPI
PchOnReadyToBoot(
  VOID
);

EFI_STATUS
EFIAPI
PchOnReadyToBootEx(
  VOID
);

EFI_STATUS
EFIAPI
PchOnExitBootServices(
  VOID
);

EFI_STATUS
EFIAPI
PchOnProtocolNotify(
  VOID
);

EFI_STATUS
EFIAPI
PchOnSmmReadyToLockNotify(
  VOID
);

EFI_STATUS
EFIAPI
PchOnSmmReadyToBootNotify(
  VOID
);

EFI_STATUS
EFIAPI
PchAcpiOnEndOfDxe(
  VOID
);

EFI_STATUS
EFIAPI
InstallPchNvsProtocol(
  VOID
);

EFI_STATUS
EFIAPI
PchUpdateNvsArea(
  VOID
);

EFI_STATUS
EFIAPI
PublishNhltAcpiTable(
  VOID
);

EFI_STATUS
EFIAPI
LockDownUnusedRstPcie(
  VOID
);

EFI_STATUS
EFIAPI
ConfigureRstPcieStorageRemapping(
  VOID
);

EFI_STATUS
EFIAPI
RstPcieStorageRemappingLateConfig(
  VOID
);

EFI_STATUS
EFIAPI
DetectPcieStorageDevices(
  VOID
);

EFI_STATUS
EFIAPI
PcieEndPointL1ssConfig(
  VOID
);

EFI_STATUS
EFIAPI
_ModuleEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
PchOnSmmCommunication(
  VOID
);

EFI_STATUS
EFIAPI
PchSteppingCheck(
  VOID
);

EFI_STATUS
EFIAPI
PchInfoLibGetPchSku(
  VOID
);

EFI_STATUS
EFIAPI
PchInfoLibGetLpcDeviceId(
  VOID
);

EFI_STATUS
EFIAPI
PchPcrRead(
  VOID
);

EFI_STATUS
EFIAPI
PchPcrWrite(
  VOID
);

EFI_STATUS
EFIAPI
PchP2sbRead(
  VOID
);

EFI_STATUS
EFIAPI
PchCycleDecodingAcpiBaseIsSet(
  VOID
);

EFI_STATUS
EFIAPI
PchCycleDecodingAcpiBaseGet(
  VOID
);

EFI_STATUS
EFIAPI
PchCycleDecodingPwrmBaseGet(
  VOID
);

EFI_STATUS
EFIAPI
UefiLibCreateReadyToBootEvent(
  VOID
);

EFI_STATUS
EFIAPI
UefiLibCreateLegacyBootEvent(
  VOID
);

EFI_STATUS
EFIAPI
GetPchPcieRpDevFun(
  VOID
);

EFI_STATUS
EFIAPI
GetPchPcieRpNumber(
  VOID
);

EFI_STATUS
EFIAPI
MemoryFreePool(
  VOID
);

EFI_STATUS
EFIAPI
MemoryStall(
  VOID
);

EFI_STATUS
EFIAPI
IoDelayShort(
  VOID
);

EFI_STATUS
EFIAPI
IoDelayEnd(
  VOID
);

EFI_STATUS
EFIAPI
Variable Definitions(
  VOID
);

EFI_STATUS
EFIAPI
core globals (set by PchInitDxeEntry)(
  VOID
);

EFI_STATUS
EFIAPI
- PCIe Segment Bus Table(
  VOID
);

EFI_STATUS
EFIAPI
PCD size(
  VOID
);

EFI_STATUS
EFIAPI
Policy HOB (from PEI phase)(
  VOID
);

EFI_STATUS
EFIAPI
list pointer(
  VOID
);

EFI_STATUS
EFIAPI
LPC bridge MMIO base(
  VOID
);

EFI_STATUS
EFIAPI
Precondition context(
  VOID
);

EFI_STATUS
EFIAPI
ACPI timer tracking(
  VOID
);

EFI_STATUS
EFIAPI
NVS Area pointer(
  VOID
);

EFI_STATUS
EFIAPI
IO Trap address(
  VOID
);

EFI_STATUS
EFIAPI
Boot Script globals(
  VOID
);

EFI_STATUS
EFIAPI
memory pool allocator(
  VOID
);

EFI_STATUS
EFIAPI
configuration table(
  VOID
);

EFI_STATUS
EFIAPI
feature enable flags(
  VOID
);

EFI_STATUS
EFIAPI
ImageHandle copy(
  VOID
);

EFI_STATUS
EFIAPI
Function Prototypes(
  VOID
);

EFI_STATUS
EFIAPI
Entry Point(
  VOID
);

EFI_STATUS
EFIAPI
1: Initialization Sequence(
  VOID
);

EFI_STATUS
EFIAPI
DxeServicesTable(
  VOID
);

EFI_STATUS
EFIAPI
PCI USRA protocol(
  VOID
);

EFI_STATUS
EFIAPI
HOB list(
  VOID
);

EFI_STATUS
EFIAPI
PCIe Segment Bus Table from PCD(
  VOID
);

EFI_STATUS
EFIAPI
debug port sequence (POST code 0x80)(
  VOID
);

EFI_STATUS
EFIAPI
POST(
  VOID
);

EFI_STATUS
EFIAPI
loop(
  VOID
);

EFI_STATUS
EFIAPI
original state(
  VOID
);

EFI_STATUS
EFIAPI
S3 boot script system(
  VOID
);

EFI_STATUS
EFIAPI
SATA RSTe Option ROM if configured(
  VOID
);

EFI_STATUS
EFIAPI
Secondary SATA RSTe Option ROM(
  VOID
);

EFI_STATUS
EFIAPI
version(
  VOID
);

EFI_STATUS
EFIAPI
Precondition(
  VOID
);

EFI_STATUS
EFIAPI
Power Management for RST Remapping(
  VOID
);

EFI_STATUS
EFIAPI
PCIe RP configuration (ASPM/L1SS)(
  VOID
);

EFI_STATUS
EFIAPI
RP Function Number mapping(
  VOID
);

EFI_STATUS
EFIAPI
device config protocol(
  VOID
);

EFI_STATUS
EFIAPI
failure(
  VOID
);

EFI_STATUS
EFIAPI
2: PCH Device Configuration(
  VOID
);

EFI_STATUS
EFIAPI
base: read PCR, set SLP_S0 and various PM registers(
  VOID
);

EFI_STATUS
EFIAPI
PMC(
  VOID
);

EFI_STATUS
EFIAPI
P2SB MMIO base and hide(
  VOID
);

EFI_STATUS
EFIAPI
each GPIO community, configure PCR pad config registers(
  VOID
);

EFI_STATUS
EFIAPI
SATA BARs, interrupt, and port enable(
  VOID
);

EFI_STATUS
EFIAPI
RP device/function(
  VOID
);

EFI_STATUS
EFIAPI
config space header(
  VOID
);

EFI_STATUS
EFIAPI
for device present (Vendor ID != 0xFFFF)(
  VOID
);

EFI_STATUS
EFIAPI
ASPM for this RP(
  VOID
);

EFI_STATUS
EFIAPI
L1SS for this RP(
  VOID
);

EFI_STATUS
EFIAPI
GPIO CLKREQ for this RP(
  VOID
);

EFI_STATUS
EFIAPI
RAID mode(
  VOID
);

EFI_STATUS
EFIAPI
SATA controller MMIO base(
  VOID
);

EFI_STATUS
EFIAPI
port power management registers(
  VOID
);

EFI_STATUS
EFIAPI
not used by RST - configure power management(
  VOID
);

EFI_STATUS
EFIAPI
per-port GPIO CLKREQ(
  VOID
);

EFI_STATUS
EFIAPI
SATA controller power management(
  VOID
);

EFI_STATUS
EFIAPI
3: USB Precondition(
  VOID
);

EFI_STATUS
EFIAPI
XHCI PCI IO protocol(
  VOID
);

EFI_STATUS
EFIAPI
XHCI MMIO base(
  VOID
);

EFI_STATUS
EFIAPI
XHCI MMIO(
  VOID
);

EFI_STATUS
EFIAPI
bus master(
  VOID
);

EFI_STATUS
EFIAPI
USB2 port count from XHCI capability registers(
  VOID
);

EFI_STATUS
EFIAPI
precondition context(
  VOID
);

EFI_STATUS
EFIAPI
port bitmap(
  VOID
);

EFI_STATUS
EFIAPI
timer handler(
  VOID
);

EFI_STATUS
EFIAPI
XHCI MMIO config(
  VOID
);

EFI_STATUS
EFIAPI
XHCI MMIO window(
  VOID
);

EFI_STATUS
EFIAPI
for ACPI timer synchronization(
  VOID
);

EFI_STATUS
EFIAPI
progressed, OK(
  VOID
);

EFI_STATUS
EFIAPI
XHCI MMIO base and program ports(
  VOID
);

EFI_STATUS
EFIAPI
port for warm reset(
  VOID
);

EFI_STATUS
EFIAPI
4: Uplink Port Programming(
  VOID
);

EFI_STATUS
EFIAPI
PCH SKU(
  VOID
);

EFI_STATUS
EFIAPI
x16 Uplink (Device ID = 0x37C0)(
  VOID
);

EFI_STATUS
EFIAPI
Max Payload Size(
  VOID
);

EFI_STATUS
EFIAPI
Max Read Size(
  VOID
);

EFI_STATUS
EFIAPI
downstream ports (function 0-5)(
  VOID
);

EFI_STATUS
EFIAPI
secondary uplink needed(
  VOID
);

EFI_STATUS
EFIAPI
x8 Uplink(
  VOID
);

EFI_STATUS
EFIAPI
x8 Uplink (Device ID = 0x37C1)(
  VOID
);

EFI_STATUS
EFIAPI
downstream port at function 2(
  VOID
);

EFI_STATUS
EFIAPI
5: ACPI NVS Protocol(
  VOID
);

EFI_STATUS
EFIAPI
NVS buffer (0x26D bytes)(
  VOID
);

EFI_STATUS
EFIAPI
signature(
  VOID
);

EFI_STATUS
EFIAPI
protocol(
  VOID
);

EFI_STATUS
EFIAPI
GPIO group info into NVS buffer(
  VOID
);

EFI_STATUS
EFIAPI
ACPI EndOfDxe processing(
  VOID
);

EFI_STATUS
EFIAPI
GPIO port config(
  VOID
);

EFI_STATUS
EFIAPI
SATA port presence(
  VOID
);

EFI_STATUS
EFIAPI
PCIe segment bus number for NVS(
  VOID
);

EFI_STATUS
EFIAPI
in PCIe RP BDF per port(
  VOID
);

EFI_STATUS
EFIAPI
PCH SKU and LPC Device ID(
  VOID
);

EFI_STATUS
EFIAPI
P2SB value(
  VOID
);

EFI_STATUS
EFIAPI
TraceHub enable flag(
  VOID
);

EFI_STATUS
EFIAPI
GPIO pad ownership(
  VOID
);

EFI_STATUS
EFIAPI
per-port GPIO pad native function status(
  VOID
);

EFI_STATUS
EFIAPI
SATA port SSD presence(
  VOID
);

EFI_STATUS
EFIAPI
SATA port with speed 20 / multiplier 2(
  VOID
);

EFI_STATUS
EFIAPI
6: ACPI EndOfDxe Processing (NHLT + NVS Patch)(
  VOID
);

EFI_STATUS
EFIAPI
HD Audio presence(
  VOID
);

EFI_STATUS
EFIAPI
NVS area(
  VOID
);

EFI_STATUS
EFIAPI
ASL update library(
  VOID
);

EFI_STATUS
EFIAPI
PCH NVS address into ASL (Name: NPCH, value: NVS base)(
  VOID
);

EFI_STATUS
EFIAPI
(INT16 *)&NvsAddr(
  VOID
);

EFI_STATUS
EFIAPI
&NvsSegment(
  VOID
);

EFI_STATUS
EFIAPI
7: NHLT ACPI Table Publishing(
  VOID
);

EFI_STATUS
EFIAPI
feature mask to set global enable flags(
  VOID
);

EFI_STATUS
EFIAPI
ACPI table protocol(
  VOID
);

EFI_STATUS
EFIAPI
NHLT endpoints(
  VOID
);

EFI_STATUS
EFIAPI
NHLT header(
  VOID
);

EFI_STATUS
EFIAPI
ACPI table(
  VOID
);

EFI_STATUS
EFIAPI
NHLT from existing RSDT/XSDT for NVS update(
  VOID
);

EFI_STATUS
EFIAPI
XSDT/RSDT for NHLT signature(
  VOID
);

EFI_STATUS
EFIAPI
NVS area with NHLT address/length(
  VOID
);

EFI_STATUS
EFIAPI
8: EndOfDxe Processing(
  VOID
);

EFI_STATUS
EFIAPI
down unused RST PCIe on primary SATA(
  VOID
);

EFI_STATUS
EFIAPI
down unused RST PCIe on secondary SATA (if present)(
  VOID
);

EFI_STATUS
EFIAPI
PCIe IO Trap address(
  VOID
);

EFI_STATUS
EFIAPI
locks in InitializePchDevice(
  VOID
);

EFI_STATUS
EFIAPI
PCIe IO Trap boot script(
  VOID
);

EFI_STATUS
EFIAPI
opcode(
  VOID
);

EFI_STATUS
EFIAPI
= UINT16(
  VOID
);

EFI_STATUS
EFIAPI
entry to boot script(
  VOID
);

EFI_STATUS
EFIAPI
hide(
  VOID
);

EFI_STATUS
EFIAPI
base disable(
  VOID
);

EFI_STATUS
EFIAPI
OS handoff in NVS area(
  VOID
);

EFI_STATUS
EFIAPI
9: Protocol Notify Callback(
  VOID
);

EFI_STATUS
EFIAPI
if PchSmmProtocol is already installed(
  VOID
);

EFI_STATUS
EFIAPI
installed, skip(
  VOID
);

EFI_STATUS
EFIAPI
Uplink ports(
  VOID
);

EFI_STATUS
EFIAPI
xHCI MMIO(
  VOID
);

EFI_STATUS
EFIAPI
PCH stepping for LPC config(
  VOID
);

EFI_STATUS
EFIAPI
TraceHub if PMC not configured(
  VOID
);

EFI_STATUS
EFIAPI
xHCI status(
  VOID
);

EFI_STATUS
EFIAPI
10: TraceHub Configuration(
  VOID
);

EFI_STATUS
EFIAPI
if TraceHub is disabled in policy(
  VOID
);

EFI_STATUS
EFIAPI
TraceHub FW_LBAR and SW_LBAR(
  VOID
);

EFI_STATUS
EFIAPI
high(
  VOID
);

EFI_STATUS
EFIAPI
low(
  VOID
);

EFI_STATUS
EFIAPI
11: SATA Lockdown(
  VOID
);

EFI_STATUS
EFIAPI
SATA (Device 23, Function 0)(
  VOID
);

EFI_STATUS
EFIAPI
SATA (Device 17, Function 5)(
  VOID
);

EFI_STATUS
EFIAPI
lockdown(
  VOID
);

EFI_STATUS
EFIAPI
12: S3 Boot Script(
  VOID
);

EFI_STATUS
EFIAPI
if boot script is already initialized (via PCD 137)(
  VOID
);

EFI_STATUS
EFIAPI
PCD to store boot script pointer(
  VOID
);

EFI_STATUS
EFIAPI
for SmmReadyToLock notification(
  VOID
);

EFI_STATUS
EFIAPI
boot script table pointer(
  VOID
);

EFI_STATUS
EFIAPI
for SMM base2 protocol(
  VOID
);

EFI_STATUS
EFIAPI
SMM boot script buffer(
  VOID
);

EFI_STATUS
EFIAPI
SMM communication handlers(
  VOID
);

EFI_STATUS
EFIAPI
13: Protocol Notify (SMM)(
  VOID
);

EFI_STATUS
EFIAPI
SMM communication for boot script(
  VOID
);

EFI_STATUS
EFIAPI
14: Helper Function Stubs(
  VOID
);

EFI_STATUS
EFIAPI
events, free buffers(
  VOID
);

EFI_STATUS
EFIAPI
PCH stepping mask(
  VOID
);

EFI_STATUS
EFIAPI
PCH PCIe RP occupies 1 device with 1 function(
  VOID
);

EFI_STATUS
EFIAPI
delay for PCH register programming(
  VOID
);

#endif /* __PCHINITDXE_H__ */