/** @file
  CpuArchDxe.h -- Header for CpuArchDxe

Copyright (c) HR650X BIOS Decompilation Project
**/

#ifndef __CPUARCHDXE_H__
#define __CPUARCHDXE_H__

#include "../uefi_headers/Uefi.h"

//
// Function Prototypes
//

EFI_STATUS
EFIAPI
Cpuid(
  VOID
);

EFI_STATUS
EFIAPI
ReadTsc(
  VOID
);

EFI_STATUS
EFIAPI
EnableInterrupts(
  VOID
);

EFI_STATUS
EFIAPI
DisableInterrupts(
  VOID
);

EFI_STATUS
EFIAPI
GetRflags(
  VOID
);

EFI_STATUS
EFIAPI
CpuHlt(
  VOID
);

EFI_STATUS
EFIAPI
CpuPause(
  VOID
);

EFI_STATUS
EFIAPI
ReadStr(
  VOID
);

EFI_STATUS
EFIAPI
ReadSldt(
  VOID
);

EFI_STATUS
EFIAPI
ReadIdtr(
  VOID
);

EFI_STATUS
EFIAPI
WriteIdtr(
  VOID
);

EFI_STATUS
EFIAPI
ReadGdtr(
  VOID
);

EFI_STATUS
EFIAPI
ReadMsr(
  VOID
);

EFI_STATUS
EFIAPI
WriteMsr(
  VOID
);

EFI_STATUS
EFIAPI
IoWrite16(
  VOID
);

EFI_STATUS
EFIAPI
IoRead32(
  VOID
);

EFI_STATUS
EFIAPI
BitFieldRead64(
  VOID
);

EFI_STATUS
EFIAPI
RShiftU64(
  VOID
);

EFI_STATUS
EFIAPI
LShiftU64(
  VOID
);

EFI_STATUS
EFIAPI
MultU64x32(
  VOID
);

EFI_STATUS
EFIAPI
DivU64x32(
  VOID
);

EFI_STATUS
EFIAPI
GetPowerOfTwo64(
  VOID
);

EFI_STATUS
EFIAPI
DivU64x64Remainder(
  VOID
);

EFI_STATUS
EFIAPI
BitFieldRead32(
  VOID
);

EFI_STATUS
EFIAPI
BitFieldOr64(
  VOID
);

EFI_STATUS
EFIAPI
InitializeFpuSse(
  VOID
);

EFI_STATUS
EFIAPI
DebugEnabled(
  VOID
);

EFI_STATUS
EFIAPI
AssertEnabled(
  VOID
);

EFI_STATUS
EFIAPI
DebugPrint(
  VOID
);

EFI_STATUS
EFIAPI
DebugAssert(
  VOID
);

EFI_STATUS
EFIAPI
EfiGetSystemConfigurationTable(
  VOID
);

EFI_STATUS
EFIAPI
AllocateZeroedPages(
  VOID
);

EFI_STATUS
EFIAPI
AllocatePool(
  VOID
);

EFI_STATUS
EFIAPI
FreePool(
  VOID
);

EFI_STATUS
EFIAPI
SetMem32(
  VOID
);

EFI_STATUS
EFIAPI
CopyMem(
  VOID
);

EFI_STATUS
EFIAPI
ZeroMem(
  VOID
);

EFI_STATUS
EFIAPI
Stall(
  VOID
);

EFI_STATUS
EFIAPI
GetMaxPhysicalAddress(
  VOID
);

EFI_STATUS
EFIAPI
MtrrSupported(
  VOID
);

EFI_STATUS
EFIAPI
GetVariableMtrrCount(
  VOID
);

EFI_STATUS
EFIAPI
GetEffectiveVariableMtrrCount(
  VOID
);

EFI_STATUS
EFIAPI
GetMtrrDefaultType(
  VOID
);

EFI_STATUS
EFIAPI
ReadAllVariableMtrrs(
  VOID
);

EFI_STATUS
EFIAPI
BuildMtrrDescriptorTable(
  VOID
);

EFI_STATUS
EFIAPI
MtrrGetMemoryAttribute(
  VOID
);

EFI_STATUS
EFIAPI
UefiBootServicesTableLibConstructor(
  VOID
);

EFI_STATUS
EFIAPI
UefiRuntimeServicesTableLibConstructor(
  VOID
);

EFI_STATUS
EFIAPI
DxeServicesTableLibConstructor(
  VOID
);

EFI_STATUS
EFIAPI
CpuArchDxeMain(
  VOID
);

EFI_STATUS
EFIAPI
DriverMainInit(
  VOID
);

EFI_STATUS
EFIAPI
ModuleEntryPoint(
  VOID
);

EFI_STATUS
EFIAPI
ProgramCpuFeatures(
  VOID
);

EFI_STATUS
EFIAPI
CacheTypeToMemoryAttribute(
  VOID
);

EFI_STATUS
EFIAPI
FindMemorySpaceMapEntry(
  VOID
);

EFI_STATUS
EFIAPI
SetMemorySpaceAttributesCpuArch(
  VOID
);

EFI_STATUS
EFIAPI
ProgramMemoryAttributes(
  VOID
);

EFI_STATUS
EFIAPI
InitExceptionHandlers(
  VOID
);

EFI_STATUS
EFIAPI
SetIdtEntry(
  VOID
);

EFI_STATUS
EFIAPI
GetExceptionTemplateInfo(
  VOID
);

EFI_STATUS
EFIAPI
SetupIdtTable(
  VOID
);

EFI_STATUS
EFIAPI
InitializeExternalInterruptHandlerTable(
  VOID
);

EFI_STATUS
EFIAPI
AcquireSpinLock(
  VOID
);

EFI_STATUS
EFIAPI
TryAcquireSpinLock(
  VOID
);

EFI_STATUS
EFIAPI
ReleaseSpinLock(
  VOID
);

EFI_STATUS
EFIAPI
MtrrSyncInit(
  VOID
);

EFI_STATUS
EFIAPI
RegisterMtrrNotify(
  VOID
);

EFI_STATUS
EFIAPI
GetPcdProtocol(
  VOID
);

EFI_STATUS
EFIAPI
DxeHobLibConstructor(
  VOID
);

EFI_STATUS
EFIAPI
GetPciExpressBase(
  VOID
);

EFI_STATUS
EFIAPI
PciExpressLibAddress(
  VOID
);

EFI_STATUS
EFIAPI
ResetColdSystem(
  VOID
);

EFI_STATUS
EFIAPI
MtrrReadDefaultType(
  VOID
);

EFI_STATUS
EFIAPI
WriteBackInvalidateCache(
  VOID
);

EFI_STATUS
EFIAPI
IsX2Apic(
  VOID
);

EFI_STATUS
EFIAPI
GetApicBase(
  VOID
);

EFI_STATUS
EFIAPI
ReadLocalApicReg(
  VOID
);

EFI_STATUS
EFIAPI
WriteLocalApicReg(
  VOID
);

EFI_STATUS
EFIAPI
GetApicMode(
  VOID
);

EFI_STATUS
EFIAPI
GetApicId(
  VOID
);

EFI_STATUS
EFIAPI
-- The EFI image handle for this driver.(
  VOID
);

/// Pointer to EFI System Table.
EFI_STATUS
EFIAPI
/// gST(
  VOID
);

/// Pointer to EFI Boot Services Table.
EFI_STATUS
EFIAPI
/// gBS(
  VOID
);

/// Pointer to EFI Runtime Services Table.
EFI_STATUS
EFIAPI
/// gRT(
  VOID
);

/// Pointer to DXE Services Table (located by GUID in .data).
EFI_STATUS
EFIAPI
/// gDS(
  VOID
);

/// PCD database pointer (located by GUID).
EFI_STATUS
EFIAPI
/// gPcdDb(
  VOID
);

/// HOB list pointer (from DxeHobLib).
EFI_STATUS
EFIAPI
/// gHobList(
  VOID
);

/// PCI Express MMIO base address.
EFI_STATUS
EFIAPI
/// gMmPciBase(
  VOID
);

/// Maximum physical address (page-aligned, CPUID-based).
EFI_STATUS
EFIAPI
/// gPhysicalMax(
  VOID
);

/// Raw maximum physical address.
EFI_STATUS
EFIAPI
/// gPhysicalMaxRaw(
  VOID
);

/// Allocated MTRR sync/state buffer (608 bytes).
EFI_STATUS
EFIAPI
/// gMtrrBuffer(
  VOID
);

/// Non-zero during MTRR sync.
EFI_STATUS
EFIAPI
/// gMtrrSyncLock(
  VOID
);

/// pointer to reserved exception vector table (22528 B).
EFI_STATUS
EFIAPI
/// gReservedVectors(
  VOID
);

/// pointer to external interrupt handler table.
EFI_STATUS
EFIAPI
/// gExternalIntHandler(
  VOID
);

/// difference: total - available variable MTRRs.
EFI_STATUS
EFIAPI
/// gVariableMtrrCountOffset(
  VOID
);

EFI_STATUS
EFIAPI
/*==========================================================================(
  VOID
);

EFI_STATUS
EFIAPI
entry: [Reserved, BaseAddress, StepSize](
  VOID
);

EFI_STATUS
EFIAPI
in sub_1E40 to iterate through fixed MTRR ranges(
  VOID
);

EFI_STATUS
EFIAPI
adjacent ranges with the same memory type.(
  VOID
);

EFI_STATUS
EFIAPI
by sub_61F to determine the correct save slot index.(
  VOID
);

EFI_STATUS
EFIAPI
during InstallMultipleProtocolInterfaces.(
  VOID
);

EFI_STATUS
EFIAPI
// gST->ConfigurationTable is at offset 112(
  VOID
);

EFI_STATUS
EFIAPI
= 10 = EfiBootServicesData(
  VOID
);

EFI_STATUS
EFIAPI
40 in gBS vtable = AllocatePages(
  VOID
);

EFI_STATUS
EFIAPI
0x80000000 to check max extended leaf(
  VOID
);

EFI_STATUS
EFIAPI
CPUID.01H:EDX[12] = MTRR support(
  VOID
);

EFI_STATUS
EFIAPI
// Check VCNT (bits 7:0) != 0(
  VOID
);

EFI_STATUS
EFIAPI
FIXED (bit 8) == 1(
  VOID
);

EFI_STATUS
EFIAPI
from pre-saved buffer (offset 80 + 2*i elements each)(
  VOID
);

EFI_STATUS
EFIAPI
Mask = ReadMsr (0x201 + 2 * i);       // IA32_MTRR_PHYSMASKi(
  VOID
);

EFI_STATUS
EFIAPI
MTRR_PHYS_MASK bit 11 (valid)(
  VOID
);

EFI_STATUS
EFIAPI
layout (32 bytes each):(
  VOID
);

EFI_STATUS
EFIAPI
0: Reserved (index)(
  VOID
);

EFI_STATUS
EFIAPI
8: BaseAddress = a4 & (mask & base)(
  VOID
);

EFI_STATUS
EFIAPI
16: Length = (a3 & ~(a4 & mask)) + 1(
  VOID
);

EFI_STATUS
EFIAPI
24: MemoryType = bits[7:0] of base(
  VOID
);

EFI_STATUS
EFIAPI
28: Attributes (0x0101 = valid + MSR pair)(
  VOID
);

/// // reads fixed MTRRs for sub-1MB addresses, then checks variable MTRRs
EFI_STATUS
EFIAPI
based on MtrrLib algorithm(
  VOID
);

EFI_STATUS
EFIAPI
addresses >= 1MB, then falls back to default type.(
  VOID
);

EFI_STATUS
EFIAPI
default(
  VOID
);

EFI_STATUS
EFIAPI
table: 11 entries, 12 bytes each =(
  VOID
);

EFI_STATUS
EFIAPI
the 11 fixed MTRR MSRs(
  VOID
);

EFI_STATUS
EFIAPI
MSR address from internal table(
  VOID
);

EFI_STATUS
EFIAPI
variable MTRRs(
  VOID
);

EFI_STATUS
EFIAPI
MTRR default type MSR(
  VOID
);

EFI_STATUS
EFIAPI
ptr at unk_8CC0 -> gDS(
  VOID
);

EFI_STATUS
EFIAPI
global services (sub_55DC equivalent)(
  VOID
);

EFI_STATUS
EFIAPI
done by constructor list(
  VOID
);

EFI_STATUS
EFIAPI
FPU + SSE (sub_410)(
  VOID
);

EFI_STATUS
EFIAPI
exception handlers (sub_12C0 / sub_4A88)(
  VOID
);

EFI_STATUS
EFIAPI
if cache is enabled (sub_243C)(
  VOID
);

EFI_STATUS
EFIAPI
GDT (sub_8EC0)(
  VOID
);

EFI_STATUS
EFIAPI
the OS-visible GDT descriptor(
  VOID
);

EFI_STATUS
EFIAPI
vector info from config table (sub_12C0)(
  VOID
);

EFI_STATUS
EFIAPI
back invalidate cache (sub_2460)(
  VOID
);

EFI_STATUS
EFIAPI
CPU Arch Protocol via gBS->InstallMultipleProtocolInterfaces(
  VOID
);

EFI_STATUS
EFIAPI
call at [BootServices + 128](
  VOID
);

EFI_STATUS
EFIAPI
GCD memory attributes based on current MTRR settings(
  VOID
);

EFI_STATUS
EFIAPI
CPU features (sub_3048)(
  VOID
);

EFI_STATUS
EFIAPI
MTRR sync (sub_1880)(
  VOID
);

EFI_STATUS
EFIAPI
back and invalidate cache(
  VOID
);

EFI_STATUS
EFIAPI
main entry(
  VOID
);

EFI_STATUS
EFIAPI
library constructor list(
  VOID
);

EFI_STATUS
EFIAPI
main entry wrapper (sub_DB0 -> sub_13A0)(
  VOID
);

EFI_STATUS
EFIAPI
failure: process destructors (sub_DA0)(
  VOID
);

/// IA32_DEBUGCTL
EFI_STATUS
EFIAPI
MSR 0x1D0(
  VOID
);

/// IA32_MISC_ENABLE
EFI_STATUS
EFIAPI
MSR 0x3A0(
  VOID
);

EFI_STATUS
EFIAPI
MSR 0x3A1(
  VOID
);

EFI_STATUS
EFIAPI
case 1:  return 2;               // WC(
  VOID
);

EFI_STATUS
EFIAPI
case 5:  return 0x1000;          // WP(
  VOID
);

EFI_STATUS
EFIAPI
}(
  VOID
);

EFI_STATUS
EFIAPI
layout at 56 bytes each:(
  VOID
);

EFI_STATUS
EFIAPI
GCD SetMemorySpaceAttributes from gDS(
  VOID
);

EFI_STATUS
EFIAPI
sync: sub_568C (1, 69639, 0, 0, 0)(
  VOID
);

EFI_STATUS
EFIAPI
max physical address(
  VOID
);

EFI_STATUS
EFIAPI
GCD memory space map via gDS(
  VOID
);

EFI_STATUS
EFIAPI
all MTRRs(
  VOID
);

EFI_STATUS
EFIAPI
GCD entries:(
  VOID
);

EFI_STATUS
EFIAPI
WB type entries (MTRR type 6)(
  VOID
);

EFI_STATUS
EFIAPI
for each WB region(
  VOID
);

EFI_STATUS
EFIAPI
adjacent ranges with same cache type in fixed MTRR region(
  VOID
);

EFI_STATUS
EFIAPI
through fixed MTRR ranges (dword_8D20 table: 11 entries x 3 DWORDs)(
  VOID
);

EFI_STATUS
EFIAPI
each MTRR range within the fixed MTRR(
  VOID
);

EFI_STATUS
EFIAPI
attribute changed, program the previous merged range(
  VOID
);

EFI_STATUS
EFIAPI
the final merged range(
  VOID
);

EFI_STATUS
EFIAPI
256 * 88 = 22528 bytes for reserved vector table(
  VOID
);

EFI_STATUS
EFIAPI
optional VectorInfo list(
  VOID
);

EFI_STATUS
EFIAPI
handler type in exception entry(
  VOID
);

EFI_STATUS
EFIAPI
external interrupt handler table (2048 bytes = 256 * 8)(
  VOID
);

EFI_STATUS
EFIAPI
current IDT limit(
  VOID
);

EFI_STATUS
EFIAPI
IDT table (4096 bytes)(
  VOID
);

EFI_STATUS
EFIAPI
exception stub template info(
  VOID
);

EFI_STATUS
EFIAPI
interrupt entry code(
  VOID
);

EFI_STATUS
EFIAPI
stubs and set vector numbers(
  VOID
);

EFI_STATUS
EFIAPI
globals and install IDT(
  VOID
);

EFI_STATUS
EFIAPI
external interrupt handler table notification(
  VOID
);

EFI_STATUS
EFIAPI
new IDTR(
  VOID
);

EFI_STATUS
EFIAPI
the MOV byte instruction encoding the vector number(
  VOID
);

EFI_STATUS
EFIAPI
stub header size = 16 bytes(
  VOID
);

EFI_STATUS
EFIAPI
handler entry at 0x430 (CommonExceptionHandler)(
  VOID
);

EFI_STATUS
EFIAPI
base (segment selector)(
  VOID
);

EFI_STATUS
EFIAPI
current CS from GDT(
  VOID
);

EFI_STATUS
EFIAPI
stub size(
  VOID
);

EFI_STATUS
EFIAPI
IDT entry:(
  VOID
);

EFI_STATUS
EFIAPI
= EntryCode + i * StubSize(
  VOID
);

EFI_STATUS
EFIAPI
= CodeSegment(
  VOID
);

EFI_STATUS
EFIAPI
= 0x8E (32-bit interrupt gate)(
  VOID
);

EFI_STATUS
EFIAPI
spin lock for exception handler(
  VOID
);

EFI_STATUS
EFIAPI
(Lock, 2, 1) == 1(
  VOID
);

EFI_STATUS
EFIAPI
to exchange from 1 (free) to 2 (acquired)(
  VOID
);

EFI_STATUS
EFIAPI
MTRR sync buffer (608 = 0x260 bytes)(
  VOID
);

EFI_STATUS
EFIAPI
protocol notify (sub_29F8)(
  VOID
);

EFI_STATUS
EFIAPI
GetPtr at offset 32 in vtable(
  VOID
);

EFI_STATUS
EFIAPI
CMOS status register A (0x4B)(
  VOID
);

EFI_STATUS
EFIAPI
CMOS status A with UIP bit set(
  VOID
);

EFI_STATUS
EFIAPI
bit 7 at the CMOS address(
  VOID
);

EFI_STATUS
EFIAPI
current RFLAGS, then disable interrupts(
  VOID
);

EFI_STATUS
EFIAPI
if interrupts were previously enabled(
  VOID
);

EFI_STATUS
EFIAPI
timer tick counter from IO port 0x508 (1288)(
  VOID
);

EFI_STATUS
EFIAPI
TSC for delay loop(
  VOID
);

EFI_STATUS
EFIAPI
for ~357ms timer tick interval(
  VOID
);

EFI_STATUS
EFIAPI
interrupt state(
  VOID
);

/// enable interrupts before WBINVD if needed
EFI_STATUS
EFIAPI
was UC(
  VOID
);

/// MMIO access
EFI_STATUS
EFIAPI
mode(
  VOID
);

EFI_STATUS
EFIAPI
ApicBaseMsr = ReadMsr (0x1B);(
  VOID
);

EFI_STATUS
EFIAPI
bit 11 (EN) is set(
  VOID
);

EFI_STATUS
EFIAPI
bit 10 (EXTD) = x2APIC(
  VOID
);

EFI_STATUS
EFIAPI
mode: CPUID.01H:EBX[31:24](
  VOID
);

EFI_STATUS
EFIAPI
mode: MSR 0x802 (x2APIC ID)(
  VOID
);

#endif /* __CPUARCHDXE_H__ */