CpuArchDxe

Index: 0056 | Size: 860668 bytes | Arch: x64 | Phase: DXE

Overview

CPU Architecture Protocol DXE driver for Purley Xeon Scalable processors. Initializes the CPU architecture protocol, sets up the IDT and exception handlers, manages MTRRs for memory attribute synchronization, programs CPU features (FPU/SSE, xAPIC/x2APIC, MWAIT), and provides spin lock primitives. This is the largest driver in the batch at ~841 KB.

Key Functions

• DriverMainInit / CpuArchDxeMain — Main initialization; programs CPU features, IDT, exception handlers, APIC, and MTRR setup
• InitExceptionHandlers — Installs 256 IDT entries with a 4096-byte IDT table and 22528-byte reserved vector table
• MtrrSyncInit — Reads all MTRRs and programs GCD memory attributes based on MTRR settings via DXE Services
• ProgramCpuFeatures — Configures IA32_DEBUGCTL, IA32_MISC_ENABLE, MWAIT, FPU/SSE (FINIT, MXCSR=0x1F80)
• ReadMsr / WriteMsr — MSR read/write wrappers with proper serialization
• AcquireSpinLock / ReleaseSpinLock / TryAcquireSpinLock — Atomic spin lock primitives via compare-exchange (1=free, 2=acquired)
• ReadLocalApicReg / WriteLocalApicReg — xAPIC/x2APIC register access (APIC base at 0xFEE00000)

Protocols / Dependencies

• CPU Architecture Protocol
• MM PCI Base protocol
• PCD protocol
• DXE Services Table (for GCD memory management)

Platform

Purley Xeon Scalable (CpuArchDxe is platform-agnostic DXE core driver)